Philips Semiconductors
Product specification
Programmable divide-by-n counter
FEATURES
•
Synchronous programmable divide-by-n counter
•
Presettable down counter
•
Fully static operation
•
Mode select control of initial decade counting function
(divide-by-10, 8, 5, 4 and 2)
•
Master preset initialization
•
Latchable output
•
Easily cascadable with other counters
•
Four operating modes:
timer
divider-by-n
divide-by-10 000
master preset
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4059 are high-speed Si-gate CMOS
devices and are pin compatible with the “4059” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4059 are divide-by-n counters which can
be programmed to divide an input frequency by any
number (n) from 3 to 15 999. There are four operating
modes, timer, divide-by-n, divide-by-10 000 and master
preset, which are defined by the mode select inputs (K
a
to
K
c
) and the latch enable input (LE) as shown in the
Function table.
The complete counter consists of a first counting stage, an
intermediate counting stage and a fifth counting stage. The
first counter stage consists of four independent flip-flops.
Depending on the divide-by-mode, at least one flip-flop is
placed at the input of the intermediate stage (the remaining
flip-flops are placed at the fifth stage with a place value of
thousands). The intermediate stage consists of three
cascaded decade counters, each containing four flip-flops.
All flip-flops can be preset to a desired state by means of
the JAM inputs (J
1
to J
16
), during which the clock input
(CP) will cause all stages to count from n to zero. The
zero-detect circuit will then cause all stages to return to the
JAM count, during which an output pulse is generated. In
the timer mode, after an output pulse is generated, the
output pulse remains HIGH until the latch input (LE) goes
LOW. The counter will advance, even if LE is HIGH and
the output is latched in the HIGH state.
74HC/HCT4059
In the divide-by-n mode, a clock cycle wide pulse is
generated with a frequency rate equal to the input
frequency divided by n.
The function of the mode select and JAM inputs are
illustrated in the following examples. In the divide-by-2
mode, only one flip-flop is needed in the first counting
section. Therefore the last (5th) counting section has three
flip-flops that can be preset to a maximum count of seven
with a place value of thousands. This counting mode is
selected when K
a
to K
c
are set HIGH. In this case input J
1
is used to preset the first counting section and J
2
to J
4
are
used to preset the last (5th) counting section.
If the divide-by-10 mode is desired for the first section, K
a
and K
b
are set HIGH and K
c
is set LOW. The JAM inputs
J
1
to J
4
are used to preset the first counting section (there
is no last counting section). The intermediate counting
section consists of three cascaded BCD decade
(divide-by-10) counters, presettable by means of the JAM
inputs J
5
to J
16
.
The preset of the counter to a desired divide-by-n is
achieved as follows:
n = (MODE
(1)
) (1 000 x decade 5 preset
+
100 x decade 4 preset
+
10 x decade 3 preset
+
1 x decade 2 preset)
+
decade 1 preset
To calculate preset values for any “n” count, divide the “n”
count by the selected mode. The resultant is the
corresponding preset value of the 5th to the 2nd decade
with the remainder being equal to the 1st decade value;
preset value = n/mode.
If n = 8 479, and the selected mode = 5, the preset
value = 8 479/5 = 1 695 with a remainder of 4, thus the
JAM inputs must be set as shown in Table 1.
To verify the results, use the given equation:
n = 5 (1 000
×
1
+
100
×
6
+
10
×
9
+
1
×
5)
+
4
n = 8 479.
If n = 12 382 and the selected mode = 8, the preset
value = 12 382/8 = 1 547 with a remainder of 6, thus the
JAM inputs must be set as shown in Table 2.
To verify:
n = 8 (1 000
×
1
+
100
×
5
+
10
×
4
+
1
×
7)
+
6
n = 12 382.
(1)
MODE = first counting section divider
(10, 8, 5, 4 or 2).
1998 Jul 08
2
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