Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer
FEATURES
•
Low “ON” resistance:
80
Ω
(typ.) at V
CC
−
V
EE
= 4.5 V
70
Ω
(typ.) at V
CC
−
V
EE
= 6.0 V
60
Ω
(typ.) at V
CC
−
V
EE
= 9.0 V
•
Logic level translation:
to enable 5 V logic to communicate
with
±
5 V analog signals
•
Typical “break before make” built in
•
Output capability: non-standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4053 are high-speed Si-gate CMOS
devices and are pin compatible with the “4053” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
QUICK REFERENCE DATA
V
EE
= GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT4053
The 74HC/HCT4053 are triple 2-channel analog
multiplexers/demultiplexers with a common enable input
(E). Each multiplexer/demultiplexer has two independent
inputs/outputs (nY
0
and nY
1
), a common input/output (nZ)
and three digital select inputs (S
1
to S
3
).
With E LOW, one of the two switches is selected (low
impedance ON-state) by S
1
to S
3
. With E HIGH, all
switches are in the high impedance OFF-state,
independent of S
1
to S
3
.
V
CC
and GND are the supply voltage pins for the digital
control inputs (S
1
, to S
3
, and E). The V
CC
to GND ranges
are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT. The
analog inputs/outputs (nY
0
and nY
1
, and nZ) can swing
between V
CC
as a positive limit and V
EE
as a negative limit.
V
CC
−
V
EE
may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V
EE
is
connected to GND (typically ground).
TYPICAL
SYMBOL
t
PZH
/ t
PZL
PARAMETER
turn “ON” time
E to V
OS
S
n
to V
OS
t
PHZ
/ t
PLZ
turn “OFF” time
E to V
OS
S
n
to V
OS
C
I
C
PD
C
S
input capacitance
power dissipation capacitance per switch notes 1 and 2
max. switch capacitance
independent (Y)
common
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+∑ {(C
L
+C
S
)
×
V
CC2
×
f
o
} where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
∑
{(C
L
+C
S
)
×
V
CC2
×
f
o
} = sum of outputs
C
L
= output load capacitance in pF; C
S
= max. switch capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
December 1990
2
(Z)
5
8
5
8
pF
pF
18
17
3.5
36
20
19
3.5
36
ns
ns
pF
pF
CONDITIONS
HC
C
L
= 15 pF; R
L
= 1 kΩ; V
CC
= 5 V
17
21
23
21
ns
ns
HCT
UNIT
PHILIPS [ NXP SEMICONDUCTORS ]
