Philips Semiconductors
Product specification
Dual 4-channel analog multiplexer,
demultiplexer
74HC4052; 74HCT4052
handbook, full pagewidth
nYn
VCC
VEE
VCC
VCC
VCC
from
logic
VEE
nZ
VEE
MNB043
Fig.6 Schematic diagram (one switch).
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to V
EE
= GND
(ground = 0 V); note 1.
SYMBOL
V
CC
I
IK
I
SK
I
S
I
EE
I
CC
; I
GND
T
stg
P
tot
P
S
Notes
1. To avoid drawing V
CC
current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the
bidirectional switch must not exceed 0.4 V. If the switch current flows into pins nZ, no V
CC
current will flow out of
pins nYn. In this case there is no limit for the voltage drop across the switch, but the voltages at pins nYn and nZ may
not exceed V
CC
or V
EE
.
2. For DIP16 packages: above 70
°C
derate linearly with 12 mW/K.
For SO16 packages: above 70
°C
derate linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60
°C
derate linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60
°C
derate linearly with 4.5 mW/K.
PARAMETER
supply voltage
input diode current
switch diode current
switch current
V
EE
current
V
CC
or GND current
storage temperature
power dissipation
power dissipation per switch
T
amb
=
−40 °C
to +125
°C;
note
V
I
< −0.5
V or V
I
>
V
CC
+ 0.5 V
V
S
< −0.5
V or V
S
>
V
CC
+ 0.5 V
−0.5
V
<
V
S
<
V
CC
+ 0.5 V
CONDITIONS
−
−
−
−
−
−65
−
−
MIN.
−0.5
MAX.
+11.0
±20
±20
±25
±20
±50
+150
500
100
V
mA
mA
mA
mA
mA
°C
mW
mW
UNIT
2004 Nov 11
6
PHILIPS [ NXP SEMICONDUCTORS ]
