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74HC4052D,652 参数 Datasheet PDF下载

74HC4052D,652图片预览
型号: 74HC4052D,652
PDF下载: 下载PDF文件 查看货源
内容描述: [74HC(T)4052 - Dual 4-channel analog multiplexer/demultiplexer SOP 16-Pin]
分类和应用: 光电二极管
文件页数/大小: 29 页 / 211 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
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74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
Rev. 10 — 19 July 2012
Product data sheet
1. General description
The 74HC4052; 74HCT4052 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4052B. The device is specified in compliance with JEDEC standard no. 7A.
The 74HC4052; 74HCT4052 is a dual 4-channel analog multiplexer/demultiplexer with
common select logic. Each multiplexer has four independent inputs/outputs (pins nY0 to
nY3) and a common input/output (pin nZ). The common channel select logics include two
digital select inputs (pins S0 and S1) and an active LOW enable input (pin E). When
pin E = LOW, one of the four switches is selected (low-impedance ON-state) with pins S0
and S1. When pin E = HIGH, all switches are in the high-impedance OFF-state,
independent of pins S0 and S1.
V
CC
and GND are the supply voltage pins for the digital control inputs (pins S0, S1 and E).
The V
CC
to GND ranges are 2.0 V to 10.0 V for the 74HC4052 and 4.5 V to 5.5 V for the
74HCT4052. The analog inputs/outputs (pins nY0 to nY3 and nZ) can swing between V
CC
as a positive limit and V
EE
as a negative limit. V
CC
V
EE
may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V
EE
is connected to GND (typically
ground).
2. Features and benefits
Wide analog input voltage range from
5
V to +5 V
Low ON resistance:
80
(typical) at V
CC
V
EE
= 4.5 V
70
(typical) at V
CC
V
EE
= 6.0 V
60
(typical) at V
CC
V
EE
= 9.0 V
Logic level translation: to enable 5 V logic to communicate with
5
V analog signals
Typical ‘break before make’ built-in
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C