Philips Semiconductors
Product specification
Phase-locked-loop with VCO
FEATURES
•
Low power consumption
•
Centre frequency of up to 17 MHz (typ.) at V
CC
= 4.5 V
•
Choice of three phase comparators: EXCLUSIVE-OR;
edge-triggered JK flip-flop;
edge-triggered RS flip-flop
•
Excellent VCO frequency linearity
•
VCO-inhibit control for ON/OFF keying and for low
standby power consumption
•
Minimal frequency drift
•
Operating power supply voltage range:
VCO section 3.0 to 6.0 V
digital section 2.0 to 6.0 V
•
Zero voltage offset due to op-amp buffering
•
Output capability: standard
•
I
CC
category: MSI.
GENERAL DESCRIPTION
Phase comparators
The 74HC/HCT4046A are high-speed Si-gate CMOS
devices and are pin compatible with the “4046” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4046A are phase-locked-loop circuits that
comprise a linear voltage-controlled oscillator (VCO) and
three different phase comparators (PC1, PC2 and PC3)
with a common signal input amplifier and a common
comparator input.
The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small
voltage signals within the linear region of the input
amplifiers. With a passive low-pass filter, the “4046A”
forms a second-order loop PLL. The excellent VCO
linearity is achieved by the use of linear op-amp
techniques.
The VCO requires one external capacitor C1 (between
C1
A
and C1
B
) and one external resistor R1 (between
R
1
and GND) or two external resistors R1 and R2
(between R
1
and GND, and R
2
and GND). Resistor R1
and capacitor C1 determine the frequency range of the
VCO. Resistor R2 enables the VCO to have a frequency
offset if required.
The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is
1997 Nov 25
2
74HC/HCT4046A
provided at pin 10 (DEM
OUT
). In contrast to conventional
techniques where the DEM
OUT
voltage is one threshold
voltage lower than the VCO input voltage, here the
DEM
OUT
voltage equals that of the VCO input. If
DEM
OUT
is used, a load resistor (R
S
) should be connected
from DEM
OUT
to GND; if unused, DEM
OUT
should be left
open. The VCO output (VCO
OUT
) can be connected
directly to the comparator input (COMP
IN
), or connected
via a frequency-divider. The VCO output signal has a duty
factor of 50% (maximum expected deviation 1%), if the
VCO input is held at a constant DC level. A LOW level at
the inhibit input (INH) enables the VCO and demodulator,
while a HIGH level turns both off to minimize standby
power consumption.
The only difference between the HC and HCT versions is
the input level specification of the INH input. This input
disables the VCO section. The sections of the comparator
are identical, so that there is no difference in the
SIG
IN
(pin 14) or COMP
IN
(pin 3) inputs between the HC
and HCT versions.
The signal input (SIG
IN
) can be directly coupled to the
self-biasing amplifier at pin 14, provided that the signal
swing is between the standard HC family input logic levels.
Capacitive coupling is required for signals with smaller
swings.
Phase comparator 1 (PC1)
This is an EXCLUSIVE-OR network. The signal and
comparator input frequencies (f
i
) must have a 50% duty
factor to obtain the maximum locking range. The transfer
characteristic of PC1, assuming ripple (f
r
= 2f
i
) is
V
CC
suppressed, is: V
DEMOUT
=
----------
( φ
SIGIN
–
φ
COMPIN
)
-
π
where V
DEMOUT
is the demodulator output at pin 10;
V
DEMOUT
= V
PC1OUT
(via low-pass filter).
V
CC
The phase comparator gain is: K
p
=
----------
(
V˙
⁄
r
)
.
-
π
The average output voltage from PC1, fed to the VCO
input via the low-pass filter and seen at the demodulator
output at pin 10 (V
DEMOUT
), is the resultant of the phase
differences of signals (SIG
IN
) and the comparator input
(COMP
IN
) as shown in Fig.6. The average of V
DEMOUT
is
equal to
1
⁄
2
V
CC
when there is no signal or noise at
SIG
IN
and with this input the VCO oscillates at the centre
frequency (f
o
). Typical waveforms for the PC1 loop locked
at f
o
are shown in Fig.7.
PHILIPS [ NXP SEMICONDUCTORS ]
