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74HC373D/T3 参数 Datasheet PDF下载

74HC373D/T3图片预览
型号: 74HC373D/T3
PDF下载: 下载PDF文件 查看货源
内容描述: [IC HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT-163-1, SOP-20, Bus Driver/Transceiver]
分类和应用: 驱动光电二极管输出元件逻辑集成电路
文件页数/大小: 26 页 / 147 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
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74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Rev. 03 — 20 January 2006
Product data sheet
1. General description
The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type
inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all latches.
The 74HC373; HCT373 consists of eight D-type transparent latches with 3-state true
outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding
D input changes.
When LE is LOW the latches store the information that was present at the D inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-
impedance OFF-state. Operation of the OE input does not affect the state of the latches.
The 74HC373; 74HCT373 is functionally identical to:
74HC533; 74HCT533: but inverted outputs
74HC563; 74HCT563: but inverted outputs and different pin arrangement
74HC573; 74HCT573: but different pin arrangement
2. Features
s
3-state non-inverting outputs for bus oriented applications
s
Common 3-state output enable input
s
Functionally identical to the 74HC563; 74HCT563, 74HC573; 74HCT573 and
74HC533; 74HCT533
s
ESD protection:
x
HBM EIA/JESD22-A114-C exceeds 2 000 V
x
MM EIA/JESD22-A115-A exceeds 200 V
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C