Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
74HC/HCT283
C
IN + (A1 + B1) + 2(A2 + B2) + +4(A3 + B3) + 8(A4 + B4) =
FEATURES
= ∑1 + 2∑2 + 4∑3 + 8∑4 + 16COUT
• High-speed 4-bit binary addition
• Cascadable in 4-bit increments
• Fast internal look-ahead carry
• Output capability: standard
• ICC category: MSI
Where (+) = plus.
Due to the symmetry of the binary add function, the “283”
can be used with either all active HIGH operands (positive
logic) or all active LOW operands (negative logic); see
function table. In case of all active LOW operands the
results ∑1 to ∑4 and COUT should be interpreted also as
active LOW. With active HIGH inputs, CIN must be held
LOW when no “carry in” is intended. Interchanging inputs
of equal weight does not affect the operation, thus CIN, A1,
B1 can be assigned arbitrarily to pins 5, 6, 7, etc.
GENERAL DESCRIPTION
The 74HC/HCT283 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
See the “583” for the BCD version.
The 74HC/HCT283 add two 4-bit binary words (An plus Bn)
plus the incoming carry. The binary sum appears on the
sum outputs (∑1 to ∑4) and the out-going carry (COUT
)
according to the equation:
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC = 5 V
C
C
C
C
IN to ∑1
IN to ∑2
IN to ∑3
IN to ∑4
16
18
20
23
21
20
20
15
ns
21
23
27
25
23
24
3.5
92
ns
ns
ns
ns
ns
ns
pF
pF
An or Bn to ∑n
IN to COUT
C
An or Bn to COUT
input capacitance
CI
3.5
88
CPD
power dissipation capacitance per package notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
December 1990
2
NXP [ NXP ]
