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74HC273 参数 Datasheet PDF下载

74HC273图片预览
型号: 74HC273
PDF下载: 下载PDF文件 查看货源
内容描述: 八路D型触发器与复位;正边沿触发 [Octal D-type flip-flop with reset; positive-edge trigger]
分类和应用: 触发器
文件页数/大小: 8 页 / 62 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
FEATURES
Ideal buffer for MOS microprocessor or memory
Common clock and master reset
Eight positive edge-triggered D-type flip-flops
See “377” for clock enable version
See “373” for transparent latch version
See “374” for 3-state version
Output capability; standard
I
CC
category: MSI
GENERAL DESCRIPTION
74HC/HCT273
The 74HC/HCT273 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT273 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q
n
) of the flip-flop.
All outputs will be forced LOW independently of clock or
data inputs by a LOW voltage level on the MR input.
The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL/
t
PLH
PARAMETER
propagation delay
CP to Q
n
MR to Q
n
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
15
15
66
3.5
20
15
20
36
3.5
23
ns
ns
MHz
pF
pF
HCT
UNIT
September 1993
2