74HC165DB-T 参数 Datasheet PDF下载

Philips Semiconductors

Product specification

8-bit parallel-in/serial-out shift register

74HC/HCT165

CE may change only from HIGH-to-LOW while CP

is LOW.

The shaded areas indicate when the input is

permitted to change for predictable output

performance.

(1) HC : V

M

= 50%; V

I

= GND to V

CC

.

HCT: V

M

= 1.3 V; V

I

= GND to 3 V.

Fig.9

Waveforms showing the set-up and hold times from the serial data input (D

s

) to the clock (CP) and clock

enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP)

to the clock enable input (CE).

(1) HC : V

M

= 50%; V

I

= GND to V

CC

.

HCT: V

M

= 1.3 V; V

I

= GND to 3 V.

Fig.10 Waveforms showing the set-up and hold times from the data inputs (D

n

) to the parallel load input (PL).

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”.

December 1990

10