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74HC165N,652 参数 Datasheet PDF下载

74HC165N,652图片预览
型号: 74HC165N,652
PDF下载: 下载PDF文件 查看货源
内容描述: [74HC165N]
分类和应用: 光电二极管逻辑集成电路触发器
文件页数/大小: 22 页 / 133 K
品牌: NXP [ NXP ]
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74HC165; 74HCT165  
8-bit parallel-in/serial out shift register  
Rev. 03 — 14 March 2008  
Product data sheet  
1. General description  
The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with  
JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).  
The 74HC165; 74HCT165 are 8-bit parallel-load or serial-in shift registers with  
complementary serial outputs (Q7 and Q7) available from the last stage. When the  
parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the  
register asynchronously.  
When PL is HIGH, data enters the register serially at the DS input and shifts one place to  
the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature  
allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the  
succeeding stage.  
The clock input is a gated-OR structure which allows one input to be used as an active  
LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary  
and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE  
should only take place while CP HIGH for predictable operation. Either the CP or the CE  
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data  
when PL is activated.  
2. Features  
I Asynchronous 8-bit parallel load  
I Synchronous serial input  
I Complies with JEDEC standard no. 7A  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
3. Applications  
I Parallel-to-serial data conversion