74HC164; 74HCT164
Philips Semiconductors
8-bit serial-in, parallel-out shift register
11. Dynamic characteristics
Table 9:
Dynamic characteristics for 74HC164
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
tPHL, tPLH propagation delay
CP to Qn
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
41
15
12
170
34
ns
ns
ns
29
tPHL
propagation delay
MR to Qn
-
-
-
39
14
11
140
28
ns
ns
ns
24
tTHL, tTLH output transition time
-
-
-
19
7
75
15
13
ns
ns
ns
6
tW
clock pulse width;
HIGH or LOW
80
16
14
14
5
-
-
-
ns
ns
ns
4
master reset pulse width; see Figure 8
LOW
VCC = 2.0 V
60
12
10
17
6
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
5
trem
removal time MR to CP
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
60
12
10
17
6
-
-
-
ns
ns
ns
5
tsu
set-up time
DSA, and DSB to CP
60
12
10
8
3
2
-
-
-
ns
ns
ns
th
hold time DSA and DSB see Figure 9
to CP
VCC = 2.0 V
+4
+4
+4
−6
−2
−2
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
fmax
maximum clock pulse
frequency
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
6
23
71
85
-
-
-
MHz
MHz
MHz
30
35
9397 750 14693
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 4 April 2005
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