Philips Semiconductors
Product specification
Dual retriggerable monostable
multivibrator with reset
FEATURES
•
DC triggered from active HIGH or
active LOW inputs
•
Retriggerable for very long pulses
up to 100% duty factor
•
Direct reset terminates output
pulse
•
Schmitt-trigger action on all inputs
except for the reset input
•
Output capability: standard (except
for nR
EXT
/C
EXT
)
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT123 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.
The 74HC/HCT123 are dual
retriggerable monostable
multivibrators with output pulse width
control by three methods. The basic
pulse time is programmed by
selection of an external resistor
(R
EXT
) and capacitor (C
EXT
). The
external resistor and capacitor are
normally connected as shown in
Fig.6.
Once triggered, the basic output
pulse width may be extended by
retriggering the gated active
LOW-going edge input (nA) or the
active HIGH-going edge input (nB).
By repeating this process, the output
pulse period (nQ = HIGH, nQ = LOW)
can be made as long as desired.
Alternatively an output delay can be
terminated at any time by a
LOW-going edge on input nR
D
, which
also inhibits the triggering.
An internal connection from nR
D
to
the input gates makes it possible to
trigger the circuit by a positive-going
signal at input nR
D
as shown in the
function table. Figures 7 and 8
illustrate pulse control by retriggering
1998 Jul 08
2
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
and early reset. The basic output
pulse width is essentially determined
by the values of the external timing
components R
EXT
and C
EXT
. For
pulse widths, when C
EXT
<
10 000 pF,
see Fig.9.
When C
EXT
>
10 000 pF, the typical
output pulse width is defined as:
t
W
= 0.45
×
R
EXT
×
C
EXT
(typ.),
74HC/HCT123
where:
t
W
= pulse width in ns;
R
EXT
= external resistor in kΩ;
C
EXT
= external capacitor in pF.
Schmitt-trigger action in the nA and
nB inputs, makes the circuit highly
tolerant to slower input rise and fall
times.
The ‘123’ is identical to the ‘423’ but
can be triggered via the reset input.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
nA, nB to nQ, nQ
nR
D
to nQ, nQ
C
I
C
PD
input capacitance
power dissipation
capacitance per
monostable
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF;
V
CC
= 5 V;
R
EXT
= 5 kΩ;
C
EXT
= 0 pF
26
20
3.5
54
HCT
26
23
3.5
56
ns
ns
pF
pF
UNIT
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑(C
L
×
V
CC2
×
f
o
) + 0.75
×
C
EXT
×
V
CC2
×
f
o
+
D
×
16
×
V
CC
where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
D = duty factor in %
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
C
EXT
= timing capacitance in pF
∑
(C
L
×
V
CC2
×
f
o
) sum of outputs
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
PHILIPS [ NXP SEMICONDUCTORS ]
