74HC123-Q100; 74HCT123-Q100
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
[3][4]
trtrig
retrigger
time
nA, nB; CEXT = 0 pF; REXT
5 k; VCC = 5.0 V;
see Figure 10
=
-
2
-
110
-
-
-
-
-
ns
REXT
CEXT
CPD
external
timing
resistor
VCC = 5.0 V; see Figure 7
VCC = 5.0 V; see Figure 7
per monostable; VI = GND
-
1000
-
-
-
-
-
-
-
-
-
-
-
-
k
pF
pF
[4]
[5]
external
timing
capacitor
-
-
-
power
-
56
dissipation to VCC
capacitance
[1] tpd is the same as tPHL and tPLH; tt is the same as tTHL and tTLH
[2] For other REXT and CEXT combinations, see Figure 7. If CEXT > 10 nF, the following formula is valid.
tW = K REXT CEXT, where:
tW = typical output pulse width in ns;
REXT = external resistor in k;
CEXT = external capacitor in pF;
K = constant = 0.45 for VCC = 5.0 V and 0.55 for VCC = 2.0 V.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is approximately 7 pF.
[3] The time to retrigger the monostable multivibrator depends on the values of REXT and CEXT. The output pulse width is only extended
when the time between the active-going edges of the trigger input pulses meets the minimum retrigger time. If CEXT >10 pF, the next
formula (at VCC = 5.0 V) for the setup time of a retrigger pulse is valid:
trtrig = 30 + 0.19 REXT CEXT0.9 + 13 REXT1.05, where:
trtrig = retrigger time in ns;
CEXT = external capacitor in pF; REXT = external resistor in k.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is 7 pF.
[4] When the device is powered-up, initiate the device via a reset pulse, when CEXT < 50 pF.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) + 0.75 CEXT VCC2 fo + D 16 VCC where:
fi = input frequency in MHz;
fo = output frequency in MHz;
D = duty factor in %;
CL = output load capacitance in pF;
VCC = supply voltage in V;
CEXT = timing capacitance in pF;
(CL VCC2 fo) sum of outputs.
74HC_HCT123_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 1 August 2012
10 of 23
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