NXP Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
4. Functional diagram
1
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2
4
2Y 6
5
9
10
12
13
mna212
&
3
&
6
3Y 8
&
8
A
4Y 11
&
mna246
11
B
Y
mna211
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
5. Pinning information
5.1 Pinning
74HC00
74HCT00
terminal 1
index area
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
8
3A
3Y
1B
1Y
2A
2B
2Y
2
3
4
5
6
7
GND
3Y
8
GND
(1)
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
3A
001aal324
© NXP B.V. 2010. All rights reserved.
74HC00
74HCT00
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
001aal323
Transparent top view
(1) The substrate is attached to this pad using conductive
die attach material. It can not be used as supply pin or
input. It is recommended that no connection is made at
all.
Fig 4.
Pin configuration DIP14, SO14 and (T)SSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
74HC_HCT00_4
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
Rev. 04 — 11 January 2010
2 of 15
Product data sheet
1
1A
PHILIPS [ NXP SEMICONDUCTORS ]
