NXP Semiconductors
TDA5051A
Home automation modem
11.2 Timing diagrams
90 % V
DD
V
DD
CLK_OUT
not defined
clock stable
DATA_IN
(1)
HIGH
TX_OUT
t
d(pu)(TX)
002aaf046
(1) DATA_IN is an edge-sensitive input and must be HIGH before starting a transmission.
Fig 10. Timing diagram during power-up in Transmission mode
90 % V
DD
V
DD
CLK_OUT
not defined
clock stable
RX_IN
DATA_OUT
not defined
HIGH
t
d(pu)(RX)
t
d(dem)(h)
002aaf047
Fig 11. Timing diagram during power-up in Reception mode
PD
DATA_IN
TX_OUT
t
d(pd)(TX)
normal operation
wrong operation
TX_OUT
delayed by PD
002aaf048
Fig 12. Power-down sequence in Transmission mode
TDA5051A
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 January 2011
13 of 29
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