Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
AC ELECTRICAL CHARACTERISTICS
(for Ceramic Dual In-Line Package)
10H20EV8: 0°C
≤
T
amb
≤
+75°C, V
EE
= –5.2V
±
5%, V
CC
= V
CO1
= V
CO2
= GND
10020EV8: 0°C
≤
T
amb
≤
+85°C, –4.8V
≤
V
EE
≤
–4.2V, V
CC
= V
CO1
= V
CO2
= GND
LIMITS
1
SYMBOL
PARAMETER
FROM
TO
MIN
2
Pulse Width
t
CKH
t
CKL
t
CKP
t
PRH
Clock High
Clock Low
Clock Period
Preset/Reset Pulse
CLK +
CLK –
CLK +
(I, I/O)
±
CLK –
CLK +
CLK +
(I, I/O)
±
2.0
2.0
4.0
4.5
—
0.6
0.9
2.0
2.0
4.0
4.5
—
0.6
0.9
2.0
2.0
4.0
4.5
—
0.6
0.9
ns
ns
ns
ns
0°C
TYP
3
MAX
2
+25°C
MIN
2
TYP
3
MAX
2
+75°C/+85°C
MIN
2
TYP
3
MAX
2
UNIT
Setup and Hold Time
t
IS
t
IH
t
PRS
Input
Input
Clock Resume after
Preset/Reset
(I, I/O)
±
CLK +
(I, I/O)
±
CLK +
(I, I/O)
±
CLK +
2.6
0.1
4.6
1.0
<0
1.0
2.6
0.1
4.6
1.1
<0
0.9
2.7
0.1
4.6
1.4
<0
0.8
ns
ns
ns
Propagation Delay
t
PD
t
CKO
t
OE
t
OD
t
PRO
t
PPR
f
MAX
Input
Clock
Output Enable
Output Disable
Preset/Reset
Power-on Reset
(I, I/O)
±
CLK +
(I, I/O)
±
(I, I/O)
±
(I, I/O)
±
V
EE
I/O
±
I/O
±
I/O
I/O
I/O
±
I/O
212
2.85
1.65
2.0
2.0
2.8
—
377
4.7
2.4
4.2
4.2
4.7
10
212
2.95
1.7
2.1
2.1
3.0
—
357
4.7
2.4
4.2
4.2
4.7
10
204
3.35
2.0
2.2
2.2
3.5
—
294
4.7
2.5
4.2
4.2
4.7
10
ns
ns
ns
ns
ns
ns
MHz
NOTES:
1. Refer to AC Test Circuit and Voltage Wafeforms diagrams.
2. Maximum loading conditions: 89 fuses intact per row.
3. Typical loading conditions: 15 fuses intact per row. (All “inactive” fuses, except those necessary for correct functionality, are removed.)
October 22, 1993
119
PHILIPS [ NXP SEMICONDUCTORS ]
