Philips Semiconductors Programmable Logic Devices
Product specification
ECL programmable array logic
10H20EV8/10020EV8
LOGIC DIAGRAM
3
0
D
0
OUTPUT
LOGIC
MACRO
CELL
4
4
8
12
INPUT LINES
16
20
24
28
32
36
7
D
0
OUTPUT
LOGIC
MACRO
CELL
21
7
1
D
0
11
2
D
0
OUTPUT
LOGIC
MACRO
CELL
5
11
9
D
0
OUTPUT
LOGIC
MACRO
CELL
20
11
10
D
0
OUTPUT
LOGIC
MACRO
CELL
7
11
11
D
0
OUTPUT
LOGIC
MACRO
CELL
18
7
OUTPUT
LOGIC
MACRO
CELL
8
13
D
0
OUTPUT
LOGIC
MACRO
CELL
17
7
14
15
16
23
22
ASYNCHRONOUS RESET
ASYNCHRONOUS PRESET
NOTES:
1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”
2.
Programmable connections
3. Pinout for F Package
October 22, 1993
114