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RL1024PAG-712 参数 Datasheet PDF下载

RL1024PAG-712图片预览
型号: RL1024PAG-712
PDF下载: 下载PDF文件 查看货源
内容描述: P系列线性光电二极管阵列成像仪 [P-SERIES LINEAR PHOTODIODE ARRAY IMAGERS]
分类和应用: 光电二极管光电二极管
文件页数/大小: 8 页 / 173 K
品牌: PERKINELMER [ PERKINELMER OPTOELECTRONICS ]
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Line a r P ho to d io d e Arra y  
Im a g e rs  
Table 2. Readout Timing Requirements  
Item  
Sym  
Min  
Typ  
Max  
ø1, ø2 clock period  
ø1, ø2 rise/fall time  
øRG rise/fall time  
øRG clock - high duration  
Delay of ø1 high - low  
transition from øRG low*  
t1  
t2  
t4  
t5  
t6  
25 ns  
-
-
-
-
-
-
-
Horizontal Shift Registers (cont.)  
5 ns  
5 ns  
-
-
ø1 and ø2. While the two-phase CCD  
shift register architecture allows  
relaxed timing tolerances over those  
required in three- or four-phase designs,  
optimum charge transfer efficiency  
and lowest power dissipation is  
5 ns  
0 ns  
-
Note: The cross over point for ø1 and ø2 clock transitions should occur within the 10 - 90ꢀ level of the clock amplitude.  
obtained when the overlap of the two-  
phase CCD clocks occurs around the  
50% transition level. Additionally, the  
phase difference between signals ø1  
and ø2 should be maintained near  
180° and the duty cycle of both signals  
should be set near 50% to prevent loss  
of full-well charge storage capacity  
and charge transfer efficiency. Readout  
timing details are shown in Figure 4  
with ranges and tolerances in Table 2.  
Table 3. Imager Performance (Typical)  
Pixel count  
512 elements (RL0512P)  
1024 elements (RL1024P)  
2048 elements (RL2048P)  
14 µm x 14 µm  
yes  
Pixel size  
Exposure control  
Horizontal clocking  
Number of outputs  
Dynamic range1  
Readout noise (rms)  
amplifier  
2Ø (5V clock amplitude)  
1
Timing Requirements  
In high-speed applications, fast  
2500:1  
waveform transitions allow maximum  
settling time of the output signal.  
However, it is generally advisable to  
use the slowest rise and fall times  
consistent with required video  
performance because fast edges tend  
to introduce more transition noise  
into the video waveform. When the  
highest speeds are required, careful  
smoothing of the waveform transitions  
may improve the balance between  
speed and video quality.  
25 electrons  
55 electrons  
60 electrons  
24 nJ/cm2  
9.6 pJ/cm2  
4 µV/electrons  
600 mv  
reset transistor  
total noise without CDS  
Saturation exposure2  
Noise equivalent exposure2  
Amplifier sensitivity  
Saturation output voltage  
Saturation charge capacity  
Charge transfer efficiency  
Peak responsivity  
150,000 electrons  
0.99995  
25V/µJ/cm2  
Output Amplifier  
Charge emerging from the last stage  
of the shift register is converted to a  
voltage signal by a charge integrator  
and video amplifier. The integrator, a  
capacitor created by a floating diffusion,  
is initially set to a DC reference volt-  
age (VRD), by setting the reset transistor  
voltage (øRG) to its high state. To read  
out the charge, øRG is pulsed low  
turning the reset transistor off and  
isolating the integrator from VRD. The  
next time ø1 goes low, the charge  
packet is transferred to the integrator  
where it generates a voltage propor-  
tional to the packet size. The reset  
transistor voltage, øRG, must reach  
its low state prior to the high-to-low  
transition of ø1. An apparent clipping  
of the video signal will result if this  
PRNU match across array  
Dead pixels  
10ꢀ  
0
Lag  
< 1ꢀ  
Spectral response range  
Data rate (per output)  
250 nm - 1000 nm  
40 MHz  
Notes:  
1. Defined as Qsat/rms noise (total).  
2. For illumination at 750 nm.  
w w w . p e r k in e lm e r . c o m / o p t o  
DSP-101 01H - 7/2002W Page 4