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PI74FCT273ATQ 参数 Datasheet PDF下载

PI74FCT273ATQ图片预览
型号: PI74FCT273ATQ
PDF下载: 下载PDF文件 查看货源
内容描述: 快速CMOS八路D触发器与主复位 [Fast CMOS Octal D Flip-Flop with Master Reset]
分类和应用: 触发器
文件页数/大小: 6 页 / 148 K
品牌: PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
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PI74FCT273T
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Fast CMOS Octal D Flip-Flop
with Master Reset
Features
• Pin compatible with bipolar FAST™ Series at a higher speed
and lower power consumption
• TTL input and output levels
• Low ground bounce outputs
• Extremely low static power
• Hysteresis on all inputs
• Industrial operating temperature range: –40°C to +85°C
• Packaging:
– 20-pin 173-mil wide plastic TSSOP (L)
– 20-pin 150-mil wide plastic QSOP (Q)
– 20-pin 300-mil wide plastic SOIC (S)
Description
Pericom Semiconductor’s PI74FCT273T is a 8-bit wide octal designed
with eight edge-triggered D-type flip-flops with individual D inputs
and O outputs. The common buffered Clock (CP) and Master Reset
(MR) load and resets (clear) all flip-flops simultaneously. The
register is fully edge-triggered. The D input state, one setup time
before the LOW-to-HIGH clock transition, is transferred to the
corresponding flip-flop's O output. All outputs will be forced LOW
independently of Clock or Data inputs by a LOW voltage level on
the MR input.
Device models available upon request.
Block Diagram
D
0
CP
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
1
D
2
D
3
D
4
D
5
D
6
D
7
MR
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Pin Configuration
MR
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
20
2
19
3
18
20-Pin
4
17
L20
5
16
Q20
6
15
S20
7
14
8
13
9
12
10
11
Pin Description
Vcc
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
Truth Table
(1)
Inputs
Mode
MR
CP
Reset (Clear) L
X
Load "1"
H
Load "0"
H
D
N
X
h
l
Outputs
O
N
L
H
L
Pin Name
MR
CP
D
0
-D
7
O
0
-O
7
GND
V
CC
Description
Master Reset (Active LOW)
Clock Pulse Input
(Active Rising Edge)
Data Inputs
Data Outputs
Ground
Power
1. H = High Voltage Level
h = High Voltage Level one setup time
prior to the LOW-to-HIGH Clock
transition
L = Low Voltage Level
l = LOW Voltage Level one setup time
prior to the LOW-to-HIGH Clock
Transition
X = Don’t Care
= LOW-to-HIGH Clock Transition
1
PS2013B
10/07/04