21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI3A125
SOT
INY
Low Voltage SPST
Analog Switch/Bus Switch
Test Circuits and Timing Diagrams
V
CC
= 2.5V ±0.2V
From Output
Under Test
C
L
= 30pF
(See Note 1)
2 x V
CC
500Ω
S1
Open
GND
500Ω
Te s t
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
Open
2 x V
CC
GND
Load Circuit
Output
Control
(Low Level
Enabling)
V
CC
V
CC
/2
0V
t
PHL
V
OH
V
CC
V
CC
/2
t
PZL
V
CC
/2
0V
t
PLZ
V
CC
V
CC
/2
V
OL
+0.15V
t
PZH
V
CC
/2
t
PHZ
V
OH
–0.15V
V
OH
0V
V
OL
Input
V
CC
/2
t
PLH
Output
Waveform 1
S1 at 2 x V
CC
(see Note 2)
Output
Waveform 2
S1 at GND
(see Note 2)
Output
V
CC
/2
V
CC
/2
V
OL
Voltage Waveforms
Propagation Delay Times
Voltage Waveforms
Propagation Delay Times
Figure 1. Test Circuit and Voltage Waveforms for V
CC
= 2.5V
Notes:
1. C
L
includes probe and jig capacitance.
2. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
3. All input pulses are supplied by generators having the following characteristics: PRR <10 MHz, Z
O
= 50Ω, t
r
≤
2ns, t
f
≤
2ns.
4. The outputs are measured one at a time with one transition per measurement.
5. t
PLZ
and t
PHZ
are the same as t
dis
.
6. t
PZL
and t
PZH
are the same as t
en
.
7. t
PLH
and t
PHL
are the same as t
pd
.
PS8575A
06/27/04
4
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
