PE4261
Product Specification
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
T
ST
T
OP
P
IN
RX input power (50
Ω)
TX input power (VSWR = (∞:1)
5,6
824-915 MHz
TX input power (VSWR = (∞:1)
5,6
1710-1910 MHz
ESD Voltage (HBM, MIL_STD
883 Method 3015.7)
ESD Voltage (MM, JEDEC,
JESD22-A114-B)
ESD Voltage (CDM, JEDEC,
JESD22-A114-B)
ESD Voltage (IEC 61000-4-2,
ANT port)
Note:
+23
+35
dBm
+33
1500
100
1500
2000
V
V
V
V
Parameter/Conditions
Power supply voltage
Voltage on any input
Storage temperature range
Operating temperature range
TX input power (50
Ω)
Min
-0.3
-0.3
-65
-40
Max
4.0
V
DD
+
0.3
+150
+85
+38
dBm
Units
V
V
°C
°C
Table 4. DC Electrical Specifications
Parameter
V
DD
Power Supply
Voltage
I
DD
Power Supply Current
(V
DD
= 2.6 V)
Control Voltage High
Control Voltage Low
0.7x V
DD
0.3x V
DD
Min
2.4
Typ
2.6
11
Max
2.8
25
Units
V
µA
V
V
Table 5. Truth Table
Path
ANT - RX1
ANT - RX2
ANT - TX1
ANT - TX2
P
IN
(∞:1)
V2
0
0
1
1
V1
0
1
0
1
V
4
ESD
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
4. ANT port rated higher per Application note, see page 10.
5. Assumes RF input duty cycle of 50% and 4620
µs.
6. V
DD
within operating range specified in Table 4.
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Table 6. Ordering Information
Order Code
PE4261-93
PE4261-96
PE4261-10
Die ID
C9804_3
C9804_3
C9804_3
Description
PE4261-DIE-D
PE4261-DIE-255G
PE4261-DIE-1H
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Package
Film Frame
Waffle Pack
Evaluation Kit
Shipping Method
Wafer (Gross Die / Wafer Quantity)
255 Dice / Waffle Pack
1 / Box
Document No. 70-0188-02
│
www.psemi.com
NDA required for full version: Contact sales@psemi.com
©2005-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 4
PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
