PE3340
Advance Information
Table 7. Primary Register Programming
Interface Mode
Serial*
Enh
1
R
5
B
0
R
4
B
1
M
8
B
2
M
7
B
3
Pre_en M
6
B
4
B
5
M
5
B
6
M
4
B
7
M
3
B
8
M
2
B
9
M
1
B
10
M
0
B
11
R
3
B
12
R
2
B
13
R
1
B
14
R
0
B
15
A
3
B
16
A
2
B
17
A
1
B
18
A
0
B
19
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface
Mode
Serial*
Enh
0
Reserved
B
0
Reserved
B
1
f
p
output
B
2
Power
down
B
3
Counter
load
B
4
MSEL
output
B
5
f
c
output
B
6
Reserved
B
7
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
MSB (first in)
(last in) LSB
Figure 4. Serial Interface Mode Timing Diagram
Sdata
E_WR
t
EC
t
CE
Sclk
S_WR
t
DSU
t
DHLD
t
ClkH
t
ClkL
t
CWR
t
PW
t
WRC
Copyright
©
Peregrine Semiconductor Corp. 2004
File No. 70/0040~02A
|
UTSi
®
CMOS RFIC SOLUTIONS
Page 8 of 12
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