PE64102
Product Specification
Serial Interface Operation and Sharing
The PE64102 is controlled by a three wire SPI-
compatible interface. As shown in
Figure 14,
the
serial master initiates the start of a telegram by
driving the SEN (Serial Enable) line high. Each bit
of the 8-bit telegram is clocked in on the rising
edge of the SCL (Serial Clock) line. SDA bits are
clocked by most significant bit (MSB) first, as
shown in
Table 5
and
Figure 14.
Transactions on
SDA (Serial Data) are allowed on the falling edge
of SCL. The DTC activates the data on the falling
edge of SEN. The DTC does not count how many
bits are clocked and only maintains the last 8 bits it
received.
More than 1 DTC can be controlled by one
interface by utilizing a dedicated enable (SEN) line
for each DTC. SDA, SCL, and V
DD
lines may be
shared as shown in
Figure 15.
Dedicated SEN
lines act as a chip select such that each DTC will
only respond to serial transactions intended for
them. This makes each DTC change states
sequentially as they are programmed.
Alternatively, a dedicated SDA line with common
SEN can be used. This allows all DTCs to change
states simultaneously, but requires all DTCs to be
programmed even if the state is not changed.
Figure 14. Serial Interface Timing Diagram (oscilloscope view)
t
EPW
t
ESU
t
DSU
t
DHD
t
R
t
F
1/f
CLK
t
EHD
SEN
SCL
SDA
b0
b7
b6
b5
b4
b3
b2
b1
b0
DTC Data
D
m-2
<7:0>
D
m-1
<7:0>
D
m
<7:0>
©2012 Peregrine Semiconductor Corp. All rights reserved.
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Document No. 70-0428-01
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