PE9702
Advance Information
Main Counter Chain
Normal Operating Mode
The main counter chain divides the RF input
frequency, F
in
, by an integer derived from the user-
defined values in the “M” and “A” counters. It is
composed of the 10/11 dual modulus prescaler,
modulus select logic, and 9-bit M counter. Setting
Pre_en
“low” enables the 10/11 prescaler. Setting
Pre_en
“high” allows F
in
to bypass the prescaler
and powers down the prescaler.
The output from the main counter chain, f
p
, is
related to the VCO frequency, F
in
, by the following
equation:
f
p
= F
in
/ [10 x (M + 1) + A]
where A
≤
M + 1, 1
≤
M
≤
511
(1)
Reference Counter
The reference counter chain divides the reference
frequency, f
r
, down to the phase detector
comparison frequency, f
c
.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
f
c
= f
r
/ (R + 1)
where 0
≤
R
≤
63
(4)
Note that programming R with “0” will pass the
reference frequency, f
r
, directly to the phase
detector.
In Direct Interface Mode, R Counter inputs R
4
and
R
5
are internally forced low (“0”). In this mode, the
R value is limited to 0
≤
R
≤
15.
Register Programming
Parallel Interface Mode
Parallel Interface Mode is selected by setting the
Bmode
input “low” and the Smode input “low”.
Parallel input data, D[7:0], are latched in a parallel
fashion into one of three 8-bit primary register
sections on the rising edge of M1_WR, M2_WR, or
A_WR per the mapping shown in Table 7 on page
10. The contents of the primary register are
transferred into a secondary register on the rising
edge of Hop_WR according to the timing diagram
shown in Figure 5. Data is transferred to the
counters as shown in Table 7 on page 10.
The secondary register acts as a buffer to allow
rapid changes to the VCO frequency. This double
buffering for “ping-pong” counter control is
programmed via the FSELP input. When FSELP is
“high”, the primary register contents set the counter
inputs. When FSELP is “low”, the secondary
register contents are utilized.
Parallel input data, D[7:0], are latched into the
enhancement register on the rising edge of E_WR
according to the timing diagram shown in Figure 4.
This data provides control bits as shown in Table 8
on page 10 with bit functionality enabled by
asserting the
Enh
input “low”.
When the loop is locked, F
in
is related to the
reference frequency, f
r
, by the following equation:
F
in
= [10 x (M + 1) + A] x (f
r
/ (R+1))
where A
≤
M + 1, 1
≤
M
≤
511
(2)
A consequence of the upper limit on A is that F
in
must be greater than or equal to 90 x (f
r
/ (R+1)) to
obtain contiguous channels. Programming the M
Counter with the minimum value of “1” will result in
a minimum M Counter divide ratio of “2”.
In Direct Interface Mode, main counter inputs M
7
and M
8
are internally forced low. In this mode, the
M value is limited to 1
≤
M
≤
127.
Prescaler Bypass Mode
Setting
Pre_en
“high” allows F
in
to bypass and
power down the prescaler. In this mode, the 10/11
prescaler and A register are not active, and the
input VCO frequency is divided by the M counter
directly. The following equation relates F
in
to the
reference frequency, f
r
:
F
in
= (M + 1) x (f
r
/ (R+1)) )
where 1
≤
M
≤
511
(3)
In Direct Interface Mode, main counter inputs M
7
and M
8
are internally forced low. In this mode, the
M value is limited to 1
≤
M
≤
127.
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 9 of 15
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