PE9303
Preliiminary Specification
Figure 2. Pin Configuration
VDD
IN
DEC
GND
1
2
8
7
GND
OUT
GND
GND
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the same
precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.
PE9303
3
4
6
5
Table 2. Pin Descriptions
Pin
No.
1
2
3
Pin
Name
VDD
IN
DEC
Description
Power supply pin. Bypassing is required.
Input signal pin. Should be coupled with a
capacitor (eg 15 pF).
Power supply decoupling pin. Place
capacitors as close as possible and
connect directly to the ground plane
(eg 10 nF & 10 pF).
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
Ground pin.
Ground pin.
Divided frequency output pin. This pin
should be coupled with a capacitor
(eg 100 pF).
Ground Pin.
Device Functional Considerations
The PE9303 takes an input signal frequency from
between 1.5 GHz to 3.5 GHz and produces an
output signal frequency one-fourth that of the
supplied input. In order for the prescaler to work
properly, several conditions need to be adhered to.
It is crucial that pin 3 be supplied with a bypass
capacitor to ground. In addition, the input and
output signals (pins 2 & 7, respectively) need to be
ac coupled via an external capacitor as shown in
the test circuit below.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance.
4
GND
5
6
7
GND
GND
OUT
8
GND
Table 3. Absolute Maximum Ratings
Symbol
VDD
T
ST
T
OP
VESD
P
INMAX
Parameter/Conditions
Supply voltage
Storage temperature
range
Operating temperature
range
ESD voltage (Human
Body Model)
Maximum input power
Min
-65
-40
Max
4.0
150
85
250
10
Units
V
°C
°C
V
dBm
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0052~01A
|
UTSi
CMOS RFIC SOLUTIONS
Page 2 of 6
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