PE83512
Product Specification
Figure 3. Pin Configuration
V
DD
IN
N/C
GND
1
2
8
7
GND
OUT
CTL
OUTB
Electrostatic Discharge (ESD) Precautions
When handling this
UTSi
device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
PE83512
3
4
6
5
Table 2. Pin Descriptions
Pin No.
1
2
3
4
Pin
Name
V
DD
4.75
Unlike conventional CMOS devices,
UTSi
CMOS
devices are immune to latch-up.
Description
Power supply pin. Bypassing is required
(eg 1000 pF & 100 pF).
Input signal pin. Should be coupled with a
capacitor (eg 1000 pF).
No connection. This pin should be left
open.
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
Inverted divided frequency output. This pin
should be coupled with a capacitor
(eg 1000 pF).
Control pin. When grounded OUTB is
enabled.
Divided frequency output pin. This pin
should be coupled with a capacitor
(eg 1000 pF).
Ground Pin.
Device Functional Considerations
The
PE83512
divides an input signal, up to a
frequency of 1500 MHz, by a factor of four
thereby producing an output frequency at one
fourth the input frequency. To work properly at
higher frequency, the input and output signals
(pins 2 , 7 & optional 5) must be AC coupled via
an external capacitor, as shown in the test circuit
in Figure 4. The input may be DC coupled for
low frequency operation with care taken to remain
within the specified DC input range for the device.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 7 for a layout example.
OUTB Control
IN
N/C
GND
5
OUTB
6
7
CTL
OUT
8
GND
Table 3. Absolute Maximum Ratings
Symbol
VDD
P
in
V
IN
T
ST
T
OP
VESD
Parameter/Conditions
Supply voltage
Input Power
Voltage on input
Storage temperature range
Operating temperature
range
ESD voltage (Human Body
Model, MIL-STD 883)
Min
Max
4.0
15
Units
V
dBm
V
°C
°C
V
-0.3
-65
-55
VDD
+0.3
150
125
2000
Pin 6 controls weather OUTB is enabled or
disabled. Pin 6 has an internal pull-up resistor.
With no connection (floating), OUTB is disabled.
By grounding pin 6, OUTB is enabled. By
enabling OUTB, this part will use roughly 5 mA
more current.
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0117~02A
|
UTSi
CMOS RFIC SOLUTIONS
Page 2 of 6
PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
