PE83336
Product Specification
Table 6. AC Characteristics
V
DD
= 3.0 V, -55° C
≤
T
A
≤
125° C, unless otherwise specified
Symbol
f
Clk
t
ClkH
t
ClkL
t
DSU
t
DHLD
t
PW
t
CWR
t
CE
t
WRC
t
EC
t
MDO
F
in
P
Fin
Parameter
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
Sdata set-up time after Sclk rising edge, D[7:0] set-up
time to M1_WR, M2_WR, A_WR, E_WR rising edge
Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge
S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge
Sclk falling edge to E_WR transition
S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge
E_WR transition to Sclk rising edge
MSEL data out delay after Fin rising edge
Operating frequency
Input level range
Conditions
Min
Typ
Max
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface and Latches (see Figures 3, 4, 5)
30
30
10
10
30
30
30
30
30
C
L
= 12 pf
500
External AC coupling
External AC coupling
-5
0
8
(Note 5)
3000
5
5
ns
MHz
dBm
dBm
Main Divider (Including Prescaler)
85°C < T
A
≤
125°C
Main Divider (Prescaler Bypassed)
F
in
P
Fin
Operating frequency
Input level range
External AC coupling
External AC coupling
50
-5
0
300
5
5
MHz
dBm
dBm
85°C < T
A
≤
125°C
Reference Divider
f
r
P
fr
V
fr
Operating frequency
Reference input power
Input sensitivity
(Note 1)
Single ended input
External AC coupling
(Note 3)
(Note 1)
100 Hz Offset: V
DD
= 3.0V, T = 25ºC
1000 Hz Offset: V
DD
= 3.0V, T = 25ºC
(Note 2)
-2
0.5
100
10
MHz
dBm
V
P-P
Phase Detector
f
c
PN
OR
PN
OR
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Comparison frequency
Output Referred Phase Noise
Output Referred Phase Noise
20
-78
-94
(Note 4)
(Note 4)
MHz
dBc/Hz
dBc/Hz
SSB Phase Noise : Output Referred (F
in
= 1918MHz, f
r
= 10 MHz, f
c
= 1MHz, LBW = 70 kHz
)
Parameter is guaranteed through characterization only and is not tested.
Running at low frequencies (< 10 MHz sinewave), the device will still be functional but may cause phase noise degradation. Inserting a low-
noise amplifier to square up the edges is recommended at lower input frequencies.
CMOS logic levels may be used if DC coupled. For optimum phase noise performance, the reference input falling edge rate should be faster
than 80mV/ns.
All devices are screened to phase noise limits listed in Table 7. The magnitude of the tester uncertainty precludes testing phase noise as part
of qualification testing. These parameters are also exempt from PDA requirements.
Parameter is tested using 100pF load capacitance and is guaranteed through characterization only. Typical test delay is 12nS.
PEREGRINE SEMICONDUCTOR CORP.
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http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 7 of 14
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