PE3512
Product Specification
Figure 3. Pin Configuration (Top View)
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 6.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
pin 1
NC
GND
IN
1
6
OUT
GND
V
DD
.
512
SC-70
2
5
3
4
Table 5. Pin Descriptions
Pin
No.
1
2
Pin
Name
N/C
GND
Device Functional Considerations
Description
No Connect. This pin should be left open.
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
Input signal pin. DC blocking capacitor
Power supply pin. Bypassing is required.
Ground pin.
Divided frequency output pin. DC blocking
3
4
5
6
IN
V
DD
GND
OUT
The
PE3512
divides an input signal, up to a
frequency of 1500 MHz, by a factor of four thereby
producing an output frequency at one-fourth the
input frequency. To work properly with low
impedance, ground referenced interfaces, the
input and output signals (pins 3 & 6) must be AC
coupled via an external capacitor, as shown in the
test circuit in Figure 4.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 9 for a layout example.
Table 6. Absolute Maximum Ratings
Symbol
V
DD
P
in
T
ST
T
OP
V
ESD
Parameter/Conditions
Supply voltage
Input Power
Storage temperature
Operating temperature
ESD voltage (Human
Min
Max
4.0
13
Units
V
dBm
°C
°C
V
-65
-40
150
85
2000
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage. Exposure
to absolute maximum ratings for extended periods
may affect device reliability.
Document No. 70-0107-03
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