PE4307
Product Specification
Figure 18. Serial Interface Timing Diagram
Table 7. 5-Bit Attenuator Serial Programming
Register Map
LE
B5
B4
B3
B2
B1
B0
Clock
0
C8
C4
C2
C1
C0.5
↑
↑
Data
MSB
LSB
MSB (first in)
LSB (last in
Note: The start bit (B5) must always be low to prevent an unknown
state in the device .
tLESUP
tLEPW
tSDSUP
tSDHLD
Figure 19. Parallel Interface Timing Diagram
LE
Parallel Data
C8:C0.5
tLEPW
tPDSUP
tPDHLD
Table 8. Serial Interface AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Table 9. Parallel Interface AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Min
Max
Unit
Symbol
tLEPW
Parameter
Min
10
Max
--
Unit
ns
Serial data clock
frequency (Note 1)
10
MHz
LE minimum pulse width
fClk
Data set-up time before
rising edge of LE
10
--
ns
tPDSUP
Serial clock HIGH time
Serial clock LOW time
30
30
10
ns
ns
ns
tClkH
tClkL
Data hold time after
falling edge of LE
10
--
ns
tPDHLD
LE set-up time after last
clock falling edge
tLESUP
tLEPW
LE minimum pulse width
30
10
ns
ns
Serial data set-up time
before clock rising edge
tSDSUP
Serial data hold time
after clock falling edge
10
ns
tSDHLD
Note:
fClk is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked
at 10 MHz to verify fclk specification.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0161-03 │ UltraCMOS™ RFIC Solutions
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