PE4307
Product Specification
Figure 15. Pin Configuration (Top View)
Table 3. Absolute Maximum Ratings
Symbol
VDD
Parameter/Conditions
Power supply voltage
Min Max Units
-0.3
-0.3
-65
-40
4.0
V
V
VDD
+
VI
Voltage on any input
0.3
1
N/C
RF1
15 C8
14
TST
Storage temperature range
150
85
°C
20-lead
QFN
Operating temperature
range
2
3
4
5
RF2
TOP
°C
13
12
11
Data
Clock
LE
P/S
4x4mm
PIN
Input power (50ꢀ)
ESD voltage (Human Body
Model)
24
dBm
V
Exposed Solder Pad
Vss/GND
GND
VESD
500
Table 4. DC Electrical Specifications
Parameter
Min
Typ
Max
Units
VDD Power Supply
Voltage
2.7
3.0
3.3
V
Table 2. Pin Descriptions
IDD Power Supply Current
Digital Input High
Digital Input Low
Input Leakage
100
µA
V
0.7xVDD
Pin
No.
Pin
Name
Description
0.3xVDD
1
V
1
2
N/C
RF1
No connect
µA
RF port (Note 1).
3
Data
Clock
LE
Serial interface data input (Note 4).
Serial interface clock input.
Latch Enable input (Note 2).
Power supply pin.
Exposed Solder Pad Connection
4
5
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
6
VDD
7
N/C
No connect
8
PUP2
VDD
Power-up selection bit.
Power supply pin.
Electrostatic Discharge (ESD) Precautions
9
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
10
11
12
GND
GND
Vss/GND
Ground connection.
Ground connection.
Negative supply voltage or GND
connection(Note 3)
13
14
P/S
RF2
C8
Parallel/Serial mode select.
RF port (Note 1).
15
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Latch-Up Avoidance
16
C4
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
17
C2
18
GND
C1
19
Attenuation control bit, 1 dB.
Attenuation control bit, 0.5 dB.
Ground for proper operation
Switching Frequency
20
C0.5
GND
The PE4307 has a maximum 25 kHz switching
rate.
Paddle
Notes: 1: Both RF ports must be held at 0 VDC or DC blocked with an
external series capacitor.
Resistor on Pin 3
2: Latch Enable (LE) has an internal 100 kꢀresistor to VDD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to VSS (-VDD) to bypass and
disable internal negative voltage generator.
A 10 kꢀ resistor on the input to Pin 3 (see Figure
5) will eliminate package resonance between the
RF input pin and the digital input. Specified
attenuation error versus frequency performance is
dependent upon this condition.
4. Place a 10 kꢀresistor in series, as close to pin as possible
to avoid frequency resonance. See “Resistor on 3”
paragraph
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0161-03 │ UltraCMOS™ RFIC Solutions
Page 2 of 11
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