PE4304
Product Specification
Figure 18. Serial Interface Timing Diagram
Table 7. 6-Bit Attenuator Serial Programming
Register Map
LE
B5
B4
B3
B2
B1
B0
Clock
C16
C8
C4
C2
C1
C0.5
↑
↑
Data
MSB
LSB
MSB (first in)
LSB (last in)
tLESUP
tLEPW
tSDSUP
tSDHLD
Figure 19. Parallel Interface Timing Diagram
LE
Parallel Data
C16:C0.5
tLEPW
tPDSUP
tPDHLD
Table 8. Serial Interface AC Characteristics
Table 9. Parallel Interface AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Min
Max
Unit
Symbol
Parameter
Min
Max
Unit
Serial data clock
frequency (Note 1)
fClk
10
MHz
tLEPW
LE minimum pulse width
10
ns
Data set-up time before
rising edge of LE
tClkH
tClkL
tLESUP
tLEPW
Serial clock HIGH time
Serial clock LOW time
30
30
ns
ns
tPDSUP
tPDHLD
10
10
ns
ns
Data hold time after
falling edge of LE
LE set-up time after last
clock falling edge
10
30
10
ns
ns
ns
LE minimum pulse width
Serial data set-up time
before clock rising edge
tSDSUP
Serial data hold time
after clock falling edge
tSDHLD
10
ns
Note:
fClk is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked
at 10 MHz to verify fclk specification.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0066-03 │ UltraCMOS™ RFIC Solutions
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