PE4302
Product Specification
Figure 17. Serial Interface Timing Diagram
LE
Table 7. 6-Bit Attenuator Serial Programming
Register Map
Clock
B5
C16
Data
MSB
LSB
B4
C8
B3
C4
B2
C2
B1
C1
B0
C0.5
↑
MSB (first in)
t
LESUP
t
LEPW
↑
LSB (last in)
t
SDSUP
t
SDHLD
Figure 18. Parallel Interface Timing Diagram
LE
Parallel Data
C16:C0.5
t
PDSUP
t
LEPW
t
PDHLD
Table 8. Serial Interface AC Characteristics
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
f
Clk
t
ClkH
t
ClkL
t
LESUP
t
LEPW
t
SDSUP
Table 9. Parallel Interface AC Characteristics
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
t
LEPW
t
PDSUP
t
PDHLD
Parameter
Serial data clock fre-
quency (Note 1)
Serial clock HIGH time
Serial clock LOW time
LE set-up time after last
clock falling edge
LE minimum pulse width
Min
Max
10
Unit
MHz
ns
ns
ns
ns
Parameter
LE minimum pulse width
Data set-up time before
rising edge of LE
Data hold time after
falling edge of LE
Min
10
10
10
Max
Unit
ns
ns
ns
30
30
10
30
Serial data set-up time
10
ns
before clock rising edge
Serial data hold time
10
ns
t
SDHLD
after clock falling edge
Note: f
Clk
is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked at
10 MHz to verify fclk specification.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 11
Document No. 70/0056~02D
│
UltraCMOS™ RFIC Solutions
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