PE4271
Product Specification
Figure 3. Pin Configuration
Table 4. DC Electrical Specifications
Parameter
Min
Typ
Max
Unit
VDD Power Supply
IDD Power Supply Current
2.7
3.0
3.3
V
VDD
GND
RF1
1
2
3
6
5
4
RF2
8
20
µA
(VDD = 3V, VCTRL = 3V)
Exposed
Solder Pad
(bottom side)
GND
CTRL
Control Voltage High
Control Voltage Low
0.7xVDD
0
5
V
V
0.3xVDD
Figure 4. Typical Application Block Diagram
Premium
Channel
Filter
PE4271
Table 2. Pin Descriptions
2-way
CATVin
CATVout
Pin
No.
Pin
Name
Splitter
Description
PE4271
1
2
3
VDD
GND
RF1
Nominal 3V supply connection.
Ground connection. 2
RF port. 1
Table 5. Control Logic Truth Table
CMOS or TTL logic level:
Control Voltage (CTRL)
Signal Path (RF1 to RF2)
4
CTRL
High = RF1 to RF2 signal path
High1
ON
Low = RF1 isolated from RF2
Ground connection. 3
RF port. 1
Low
OFF
5
6
GND
RF2
Notes: 1. CTRL accepts both CMOS and TTL voltage leads.
Notes: 1. Both RF pins must be held at 0 VDC or require external DC
blocking capacitors
Electrostatic Discharge (ESD) Precautions
2. The exposed pad must be soldered to the ground plane for
proper switch performance.
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Table 3. Absolute Maximum Ratings
Symbol Parameter/Condition
Min
-0.3
-0.3
-65
Max
4.0
5.5
150
85
Unit
V
V
°C
°C
VDD
VI
Power supply voltage
Voltage on CTRL input
Storage temperature
Operating temperature
Device Description
TST
TOP
-40
The PE4271 high isolation SPST CATV Switch is
designed to support CATV applications such as
premium channel service connect/disconnect switch
blocks. This function is typically performed by bulky
and expensive mechanical switches. The high
isolation characteristics (60 dB at 1 GHz, 85 dB at
5 MHz), high compression point, and an integrated
75 ꢀ (0.25 watt) input termination make the PE4271
an ideal, low cost solution.
Input power (50ꢀ),
PIN
33/24
500
dBm
V
CTRL=1/CTRL=0
ESD voltage
VESD
(Human Body Model)
Absolute Maximum Ratings are those values listed
in the above table. Exceeding these values may
cause permanent device damage. Functional
operation should be restricted to the limits in the DC
Electrical Specifications table. Exposure to absolute
maximum ratings for extended periods may affect
device reliability.
The control logic input pin (CTRL) is typically driven
by a 3-volt CMOS logic level signal, and has a
threshold of 50% of VDD. For flexibility to support
systems that have 5-volt control logic drivers, the
control logic input has been designed to handle a 5-
volt logic HIGH signal. (A minimal current will be
sourced out of the VDD pin when the control logic
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
input voltage level exceeds VDD.
)
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0149-03 │ UltraCMOS™ RFIC Solutions
Page 2 of 8
PSEMI [ Peregrine Semiconductor ]
