PE4240
Product Specification
Figure 3. Pin Configuration
RF2
GND
RF1
1
2
3
Exposed Solder
Pad - Shorted
to Pin 2
(bottom side)
Table 4. DC Electrical Specifications @ 25 °C
Parameter
Min
2.7
Typ
3.0
33
Max
3.3
40
5
30% V
DD
Unit
V
µA
V
V
6
5
4
RFC
CTRL
V
DD
Power Supply
I
DD
Power Supply Current
(V
DD
= 3V, V
CNTL
= 3V)
Control Voltage High
70% V
DD
0
V
DD
Control Voltage Low
Table 2. Pin Descriptions
Pin
No.
1
2
3
4
5
6
Pin
Name
V
DD
GND
RF1
CTRL
GND
RF2
Description
Nominal 3 V supply connection.
1
Ground connection.
3
RF port.
2
CMOS or TTL logic level:
High = RF1 to RF2 signal path
Low = RF1 isolated from RF2
Ground connection.
3
RF port.
2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Device Description
The PE4240 high isolation SPST CATV Switch is
designed to support CATV applications such as
premium channel service connect/disconnect switch
blocks. This function is typically performed by bulky
and expensive mechanical switches. The high
isolation characteristics (>44 dB at 1 GHz, 85 dB
at 5 MHz), high compression point, and an
integrated 75-ohm terminations make the PE4240
an ideal, low cost solution.
Figure 4. Typical Application Block Diagram
Unit
V
V
°C
°C
dBm
V
2-way
Splitter
PE4240
Premium
Channel
Filter
PE4240
Notes: 1. A bypass capacitor should be placed as close as possible
to the pin.
2. Both RF pins must be held at 0 V
AC
or require external DC
blocking capacitors.
3. The exposed pad must be soldered to the ground plane for
proper switch performance.
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
T
ST
T
OP
P
IN
V
ESD
Parameter/Condition
Power supply voltage
Voltage on CTRL input
Storage temperature
Operating temperature
Input power (50Ω),
CTRL=1/CTRL=0
ESD voltage
(Human Body Model)
Min
-0.3
-0.3
-65
-40
Max
4.0
5.5
150
85
33/24
200
CATVin
CATVout
Table 5. Control Logic Truth Table
Control Voltage (CTRL)
High
1
Low
Signal Path (RF1 to RF2)
ON
OFF
Absolute Maximum Ratings are those values listed
in the above table. Exceeding these values may
cause permanent device damage. Functional
operation should be restricted to the limits in the DC
Electrical Specifications table. Exposure to absolute
maximum ratings for extended periods may affect
device reliability.
Notes: 1. CTRL accepts both CMOS and TTL voltage leads.
The control logic input pin (CTRL) is typically driven
by a 3-volt CMOS logic level signal, and has a
threshold of 50% of V
DD
. For flexibility to support
systems that have 5-volt control logic drivers, the
control logic input has been designed to handle a 5-
volt logic HIGH signal. (A minimal current will be
sourced out of the V
DD
pin when the control logic in-
put voltage level exceeds V
DD.
)
Document No. 70-0067-03
│
UltraCMOS™ RFIC Solutions
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 8
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