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4231-02 参数 Datasheet PDF下载

4231-02图片预览
型号: 4231-02
PDF下载: 下载PDF文件 查看货源
内容描述: SPDT大功率的UltraCMOS - DC 1.3 GHz的RF开关 [SPDT High Power UltraCMOS - DC 1.3 GHz RF Switch]
分类和应用: 开关光电二极管
文件页数/大小: 7 页 / 272 K
品牌: PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
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PE4231
Product Specification
Figure 3. Pin Configuration (Top View)
Table 4. DC Electrical Specifications
Parameter
Min
2.7
Typ
3.0
29
Max
3.3
35
Units
V
µA
V
V
DD
CTRL
1
2
8
7
RF1
GND
V
DD
Power Supply
Voltage
I
DD
Power Supply Current
(V
DD
= 3V, V
CNTL
= 3V)
Control Voltage High
4231
GND
3
4
6
5
GND
0.7xV
DD
0.3xV
DD
Control Voltage Low
RFCommon
RF2
V
Table 2. Pin Descriptions
Pin
No.
1
2
Table 5. Truth Table
Control Voltage
Signal Path
RFCommon to RF1
RFCommon to RF2
Pin Name
V
DD
CTRL
Description
Nominal +3 V supply connection.
CMOS or TTL logic level:
High = RFCommon to RF1 signal path
Low = RFCommon to RF2 signal path
Ground connection. Traces should be
physically short and connected to ground
Common RF port for switch.
1
RF2 port.
1
Ground Connection. Traces should be
physically short and connected to ground
Ground Connection. Traces should be
physically short and connected to ground
RF1 port.
1
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
3
GND
4
5
6
RF Common
RF2
GND
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of V
DD
. For flexibility to
support systems that have 5-volt control logic
drivers, the control logic input has been designed
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the V
DD
pin when the
control logic input voltage level exceeds V
DD
.)
Latch-Up Avoidance
7
GND
8
RF1
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Note 1: All RF pins must be DC blocked with an external
series capacitor or held at 0 V
DC
.
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
V
CTRL
T
ST
T
OP
P
IN
V
ESD
Parameter/
Conditions
Power supply voltage
Voltage on any input ex-
cept for the CTRL input
Voltage on CTRL input
Storage temperature
range
Operating temperature
range
Input power (50Ω)
ESD voltage (Human
Body Model)
Min
-0.3
-0.3
Max
4.0
V
DD
+
0.3
5.0
Units
V
V
V
°C
°C
dBm
V
-65
-40
150
85
33
200
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 7
Document No. 70-0097-01
UltraCMOS™ RFIC Solutions