PE3340
Advance Information
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Reserved**
Reserved**
f
p
output
Power down
Counter load
MSEL output
f
c
output
Reserved**
Drives the M counter output onto the Dout output.
Power down of all functions except programming interface.
Immediate and continuous load of counter programming.
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Drives the reference counter output onto the Dout output
Description
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (f
p
) and the reference
counter (f
c
). It has two outputs, namely PD_U, and
PD_D. If the divided VCO leads the divided
reference in phase or frequency (f
p
leads f
c
), PD_D
pulses “low”. If the divided reference leads the
divided VCO in phase or frequency (f
c
leads f
p
),
PD_U pulses “low”. The width of either pulse is
directly proportional to phase offset between the
two input signals, f
p
and f
c
.
The phase detector gain is equal to 2.70 V / 2
π,
which numerically yields 0.43 V / Radian.
PD_U and PD_D drive an active loop filter which
controls the VCO tune voltage. PD_U pulses result
in an increase in VCO frequency and PD_D results
in a decrease in VCO frequency, for a positive Kv
VCO.
A lock detect output, LD is also provided, via the pin
Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kohm resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal
inverting comparator with an open drain output.
Thus LD is an “AND” function of PD_U and PD_D.
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©
Peregrine Semiconductor Corp. 2004
Page 9 of 12
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