PE3336
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
(44-lead PLCC)
28
29
30
Pin No.
(48-lead QFN)
23
24
25
Pin
Name
F
in
GND
f
p
Interface
Mode
ALL
ALL
ALL
Type
Description
Prescaler complementary input. A bypass capacitor should be
placed as close as possible to this pin and be connected in
series with a 50
Ω
resistor directly to the ground plane.
Ground.
Input
Output
Monitor pin for main divider output. Switching activity can be
disabled through enhancement register programming or by
floating or grounding V
DD
pin 31.
V
DD
for f
p
. Can be left floating or connected to GND to disable
the f
p
output.
Data Out. The MSEL signal and the raw prescaler output are
available on Dout through enhancement register
programming.
Same as pin 1.
Logical “NAND” of PD_U and PD_D terminated through an on
chip, 2 kΩ series resistor. Connecting Cext to an external
capacitor will low pass filter the input to the inverting amplifier
used for driving LD.
Same as pin 1.
PD_D is pulse down when f
p
leads f
c
.
PD_U is pulse down when f
c
leads f
p
.
31
26
V
DD
-f
p
ALL
Serial,
Parallel
ALL
(Note 1)
32
33
27
28
Dout
V
DD
Output
(Note 1)
34
29
Cext
ALL
Output
35
36
37
38
30
32
33
35
V
DD
PD_D
PD_U
V
DD
-f
c
ALL
ALL
ALL
ALL
(Note 1)
Output
(Note 1)
V
DD
for f
c
can be left floating or connected to GND to disable
the f
c
output.
Monitor pin for reference divider output. Switching activity can
be disabled through enhancement register programming or by
floating or grounding V
DD
pin 38.
Ground.
Ground.
39
40
41
42
43
36
31,37
38,39
40
41
42
34
f
c
GND
GND
f
r
LD
Enh
NC
ALL
ALL
ALL
ALL
ALL
Serial,
Parallel
ALL
Output
Input
Output
Reference frequency input.
Lock detect and open drain logical inversion of CEXT. When
the loop is in lock, LD is high impedance, otherwise LD is a
logic low (“0”).
Enhancement mode. When asserted low (“0”), enhancement
register bits are functional.
No connection.
44
N/A
Note 1:
Input
All V
DD
pins are connected by diodes and must be supplied with the same positive voltage level.
V
DD
-f
p
and V
DD
-f
p
are used to power the f
p
and f
c
outputs and can alternatively be left floating or connected to GND to disable the f
p
and f
c
outputs.
Note 2:
All digital input pins have 70 kΩ pull-down resistors to ground.
Document No. 70-0033-02
│
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©2005 Peregrine Semiconductor Corp. All rights reserved.
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