PE3336
Product Specification
Figure 2. Pin Configurations (Top View)
GND
GND
GND
Enh
V
DD
LD
R
3
R
2
R
1
R
0
fr
GND
GND
GND
GND
Enh
V
DD
LD
R3
R2
R1
R0
6
D
0
, M
0
D
1
, M
1
D
2
, M
2
D
3
, M
3
V
DD
V
DD
S_WR, D
4
, M
4
Sdata, D
5
, M
5
Sclk, D
6
, M
6
FSELS, D
7
, Pre_en
GND
5
4
3
2
1
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
f
c
V
DD
_f
c
PD_U
PD_D
V
DD
C
ext
V
DD
D
out
V
DD
_f
p
f
p
GND
D0, M0
D1, M1
D2, M2
D3, M3
V
DD
V
DD
S_W R, D4, M4
Sdata, D5, M5
Sclk, D6, M6
FSELS, D7, Pre_en
GND
48 47 46 45 44 43 42 41 40 39 38 37
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
1
2
3
4
5
6
7
8
9
10
11
f
r
36
35
34
33
32
31
30
29
28
27
26
25
f
c
V
DD
_f
c
NC
PD_U
PD_D
GND
V
DD
C
ext
V
DDE
D
out
V
DD
_f
p
f
p
FSELP, A0
12
13 14 15 16 17 18 19 20 21 22 23 24
E_WR, A1
M2_WR, A2
Smode, A3
Bmode
V
DD
V
DD
M1_WR
A_WR
Hop_WR
Fin
Fin
GND
Table 1. Pin Descriptions
Pin No.
(44-lead PLCC)
1
2
3
4
5
6
7
FSELP, A
0
E_WR, A
1
44-lead PLCC
(48-lead QFN)
43
44
45
46
47
48
1
M2_WR, A
2
Pin No.
Smode, A
3
Bmode
V
DD
M1_WR
V
DD
R
0
R
1
R
2
R
3
GND
D
0
M
0
D
1
A_WR
Pin
Name
Hop_WR
F
in
F
in
48-lead QFN
Interface
Mode
ALL
Direct
Direct
Direct
Direct
ALL
Parallel
Direct
Parallel
Direct
Parallel
Direct
Parallel
Direct
ALL
ALL
Type
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
(Note 1)
Description
Power supply input. Input may range from 2.85 V to 3.15 V.
Bypassing recommended.
R Counter bit0 (LSB).
R Counter bit1.
R Counter bit2.
R Counter bit3.
Ground.
Parallel data bus bit0 (LSB).
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
Parallel data bus bit2.
M Counter bit2.
Parallel data bus bit3.
M Counter bit3.
Same as pin 1.
Same as pin 1.
8
2
M
1
D
2
9
3
M
2
D
3
10
11
12
4
M
3
5
6
V
DD
V
DD
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 15
Document No. 70-0033-02
│
UltraCMOS™ RFIC Solutions
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