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3335-23 参数 Datasheet PDF下载

3335-23图片预览
型号: 3335-23
PDF下载: 下载PDF文件 查看货源
内容描述: 3000兆赫UltraCMOS⑩整数N分频PLL的低相位噪声应用 [3000 MHz UltraCMOS⑩ Integer-N PLL for Low Phase Noise Applications]
分类和应用:
文件页数/大小: 15 页 / 235 K
品牌: PSEMI [ Peregrine Semiconductor ]
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PE3335  
Product Specification  
Enhancement Register  
The functions of the enhancement register bits are shown below with all bits active “high”.  
Table 9. Enhancement Register Bit Functionality  
Bit Function  
Description  
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Reserved**  
Reserved**  
Reserved**  
Power down  
Counter load  
Power down of all functions except programming interface.  
Immediate and continuous load of counter programming as directed by the Bmode and  
Bit 5  
Bit 6  
Bit 7  
MSEL output  
Prescaler output  
fp, fc OE  
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.  
Drives the raw internal prescaler output onto the Dout output.  
fp, fc outputs disabled.  
** Program to 0  
Phase Detector  
The phase detector is triggered by rising edges  
from the main Counter (fp) and the reference  
counter (fc). It has two outputs, PD_U, and PD_D.  
If the divided VCO leads the divided reference in  
phase or frequency (fp leads fc), PD_D pulses  
“low”. If the divided reference leads the divided  
VCO in phase or frequency (fc leads fp), PD_U  
pulses “low”. The width of either pulse is directly  
proportional to phase offset between the two input  
signals, fp and fc.  
CP. The current pulses from pin CP are low pass  
filtered externally and then connected to the VCO  
tune voltage. PD_U pulses result in a current  
source, which increases the VCO frequency;  
PD_D pulses result in a current sink, which  
decreases VCO frequency (for a positive Kv  
VCO).  
A lock detect output, LD is also provided, via the  
pin Cext. Cext is the logical “NAND” of PD_U and  
PD_D waveforms, which is driven through a series  
2 kohm resistor. Connecting Cext to an external  
shunt capacitor provides low pass filtering of this  
signal. Cext also drives the input of an internal  
inverting comparator with an open drain output.  
Thus LD is an “AND” function of PD_U and PD_D.  
The signals from the phase detector couple  
directly to a charge pump. PD_U controls a  
current source at pin CP with constant amplitude  
and pulse duration approximately the same as  
PD_U. PD_D similarly drives a current sink at pin  
Document No. 70-0049-02 www.psemi.com  
©2005 Peregrine Semiconductor Corp. All rights reserved.  
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