AN8032
s
Application Notes (continued)
[2] Operation description (continued)
1. Normal control (continued)
3) Description of each function (continued)
Voltage Regulators
(4)
EI/EO
The resisitance-devided voltage of the active filter output is input to the EI. The EI is the error
amplifier's inverted input, and the temperature-compensated reference voltage (2.5 V typical) is input as
the noninverted input. The error amplifier amplifies the error amount between the output voltage, and the
reference voltage and outputs to the multiplier. The resistor between the EI and EO is used for determin-
ing the gain of error amplifier.
As for the resistance-dividing for decreasing the active filter's output voltage to the input D-range of
EI, if an attempt is made to use a small-sized resistor for suppressing the dissipation, its resistance value
becomes high because of the high output voltage. For this reason, note that if the capacitance inserted
between the EI and EO for phase compensation is large, the delay element between it and the resistance-
divider of high resistance becomes large, so that the characteristics at the time of sudden change of load
(overshoot or undershoot) is degraded.
Therefore, as the value for phase compensation capacitor, select the minimum value with which the
oscillation can be prevented.
Output
Error amplifier
4
EI
SBD
To multiplier
Reference voltage
(2.5 V typ.)
Resistor determining the gain
EO
3
Phase compensation capacitor
Figure 7. EI/EO terminal description
(5)
V
OUT
For the drive circuit, the AN8032 employs the totem pole type by which the power MOSFET can be
directly driven. Since the peak output current is
±1
A, the TO-220 class power MOSFET can be driven.
For the TOP-3 class, the buffer circuit should be added outside because its capability is not sufficient for
that class.
The power MOSFET momentarily swings to minus due to the parasitic capacitance between the
drain and gates at the time of turn-off and this causes malfunction in some cases. Therefore, the Schottky
barrier diode should be inserted between the V
OUT
and GND if necessary.
Power
MOSFET
PV
CC
Totem pole type
output circuit
Off
On
V
D
Parasitic
capacitance
0V
V
D
V
G
V
G
0V
Swing to negative voltage
Figure 8.
V
OUT
terminal description
Capacitive coupling
V
OUT
GND
12
PANASONIC [ PANASONIC SEMICONDUCTOR ]
