AN8027, AN8037
Voltage Regulators
■ Application Notes (continued)
[1] Operation descriptions (continued)
6. Notes on the feedback control (continued)
[Countermeasures]
If an application exhibits the symptoms of the case described above, or similar symptoms, first insert a Schottky
barrier diode between VOUT and GND. It is not possible to completely remove the mechanism described above from
a power supply system. It is also not possible to prevent levels from being pulled down to negative voltages in the
control IC itself. Therefore, the most important point in designing countermeasures is to prevent such negative
voltages from reaching the parasitic device conductance voltage.
Note) If a Schottky barrier diode is added to the circuit and the condition improves initially but the symptoms reappear when
the input voltage or other parameter is increased, try replacing the Schottky barrier diode with one that has a larger
forward current (both peak and average values). The current capacity of the Schottky barrier diode is sometime
insufficient.
(Reference)
The following our Schottky diodes are available.
Part No.
Reverse voltage Forward current (average) Forward current (peak)
MA2C700A (MA700A*)
MA2C723 (MA723*)
MA2C719 (MA719*)
30 V
30 V
40 V
30 mA
200 mA
500 mA
150 mA
300 mA
1 A
Note) : Former part number
*
7. Local resonance operation (power MOSFET turn-on delay circuit)
Local resonance operation by using the AN8027 or AN8037 is possible with circuits as shown in figure 13.
C7 is the resonance capacitor, and R9 and C9 form a delay circuit for adjusting the power MOSFET turn on time.
When the power MOSFET is off, the voltage that occurs in the drive winding is input to the TR pin (pin 1)
through R9 and C9. The power MOSFET will be held in the off state while a high level (a level higher than the
threshold voltage, which is 0.25 V typical) is input to the TR pin.
The TR pin also has a clamping capability for upper and lower limit voltages. The upper limit voltage is clamped
at 0.7 V (typical) (sink current: −3 mA), and the lower limit voltage is clamped at about − 0.15 V typical (source
current: 3 mA). (Refer to figure 11.)
The power MOSFET off-period is determined by the longer period of the following two periods: the period
until the TR pin input voltage becomes lower than the threshold voltage as the bias winding voltage falls after the
transformer discharges its energy, and the minimum off-period (TOFF(min)) stipulated by the internal oscillator.
(Refer to the "Setting the off-period" section in the "Operating descriptions, 2. Oscillation circuit.") As a result,
ringing in the bias winding does not be regarded as a turn on signal during the minimum off-period.
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PANASONIC [ PANASONIC ]
