ICs for TV
AN5394FB
■ Electrical Characteristics at VCC = 9 V, VCC = 5 V, Ta = 25°C (continued)
The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
(4) OSD, RGB (continued)
Ym rising delay
Symbol
Conditions
Min
Typ Max
Unit
trYm
tfYm
trRGB
tfRGB
22
20
ns
ns
Ym falling delay
RGB rising delay
28
ns
RGB falling delay
43
ns
Pedestal change at Ys changeover ∆VP(Ys) Ys: Low → varying amount of high
Pedestal change at Ym changeover ∆VP(Ym) Ym: Low → varying amount of high
Pedestal change at RGB changeover ∆VP(RGB) RGB: Low → varying amount of high
−40
−40
−40
−50
mV
mV
mV
mV
Pedestal change at
∆VP
(RGB+Ym)
RGB, Ym: Low → varying amount of
RGB+Ym changeover
high
OSD input dynamic range
DOSD
1.5
V[p-p]
%
OSD output amplitude
ambient temp. dependency
OSD
∆T
−20°C to +70°C
−20°C to +70°C
±2
RGB input dynamic range
DRGB
1.5
V[p-p]
%
RGB output amplitude
RGB
±2
ambient temp. dependency
∆T
R, B-in clamp voltage
variable range
∆VCLP
R-in, B-in−DC adj
min. → max.
200
mV
(5) Cutoff drive
Blanking delay
tdBLK(1) From BLK to BLK output
45
0
ns
Pedestal fluctuation at contrast ∆VP(CONT) Contrast: min. → max.
mV
variation
Pedestal fluctuation
at color variation
∆VP(COLOR) Contrast: min. → max.
0
mV
Pedestal fluctuation at tint variation ∆VP(TNIT)
0
mV
Output pedestal potential
ambient temp. dependency
∆VP
∆T
−20°C to +70°C
−1.5
mV/°C
Spot killer operation
VSP
Lowering 9V system VCC
7.8
V
Pin 29: C = 10 µF
(6) I2C DAC
4 · 5 · 6DAC
DNLE
L1
L2
L3
L4
L5
1LSB = {DAT (max.)
− data(min.)}/(2N−1)
0.1
0.1
1.0
1.0
1.0
1.0
1.0
1.9
1.9
2.0
1.9
2.0
LSB
STep
8-bit DAC DNLE
(excluding 40, 80, CO)
1LSB = {DAT (max.)
− data(min.)}/(2N−1)
LSB
STep
8-bit DAC DNLE
(for 40, 80, CO only)
1LSB = {DAT (max.)
− data(min.)}/(2N−1)
−1.0
0.1
LSB
STep
7-bit DAC DNLE
(excluding 40)
1LSB = {DAT (max.)
− data(min.)}/(2N−1)
LSB
STep
7-bit DAC DNLE
(for 40 only)
1LSB = {DAT (max.)
− data(min.)}/(2N−1)
−1.0
LSB
STep
11