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AN5195K-C 参数 Datasheet PDF下载

AN5195K-C图片预览
型号: AN5195K-C
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片集成电路为PAL / NTSC彩电(内置I2C总线接口) [Single chip IC for PAL/NTSC color TV (built-in I2C bus interface)]
分类和应用: 电视
文件页数/大小: 26 页 / 309 K
品牌: PANASONIC [ PANASONIC SEMICONDUCTOR ]
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AN5195K-C
s
Electrical Characteristics at T
a
=
25°C (continued)
Parameter
Symbol
Conditions
Min
1.31
50
4.5
0.8
4.1
Typ
1.41
100
5.0
1.3
4.6
ICs for TV
Max
Unit
Chroma signal processing circuit (continued)
CW output level (3.58 MHz)
CW output level period (SECAM)
SECAM discrimination current
SECAM discrimination output
PAL/NTSC DC level
SECAM DC level
RGB processing circuit
Drive adjustment range
Cut-off adjustment range
Y
S
threshold voltage
Y
S
threshold voltage
Internal and external pedestal
difference voltage
External RGB output voltage
V
CWN
T
CW
I
SECAM
V
SE
V
59PN
V
59S
G
DV
V
CUTOFF
V
YSON
V
YSOFF
∆V
PL/IE
V
ERGB
Burst 150 mV[p-p] (PAL), reference is B-out
50
1.51
150
1.65
5.1
mV[p-p]
ms
µA
V
V
V
AC component, when V
CO
is set at 3.58 MHz
CW output period at SECAM and PAL
Minimum value for taking out current
from pin 59 and discriminating as SECAM
V
5
data, when SECAM signal inputted
0A−D6
=
1, 0A−D7
=
0, SECAM det. out
V
59
DC level at PAL/NTSC
V
59
DC level at SECAM
AC change amount of R, B-out,
when drive adjustment max. and min.
DAC data are typical
5
6
2.4
0
0
2.2
1.0
17
10
0.92
7
2.7
0.4
200
200
2.7
1.2
22
1.06
dB
V
V
V
mV
mV
V[p-p]
Times
dB
MHz
Times
DC change amount of R,G,B-out,
2.1
when cutoff adjustment max. and min.
Minimum DC voltage, when Y
S
turns on 1.0
Maximum DC voltage, when Y
S
turns off
Y
S
=
5 V
Internal-external
Input 0.7 V[p-p], contrast 03
=
20 (typ.)
Output ratio of external R,G,B-out
03
=
3F
03
=
00
Input 0.2 V[p-p]
External 0.7 V[p-p]/internal 0.6 V[p-p]
input, contrast 03
=
20 (typ.)
−200
200
1.8
0.8
12
8
0.78
External RGB pedestal difference voltage
∆V
EPL
External RGB output difference voltage
∆V
ERGB
External RGB contrast variable E
Cmax/min
range
External RGB frequency characteristics f
RGBC
Internal and external RGB
output voltage ratio
V
E/I
Synchronizing signal processing circuit
Horizontal free-running
oscillation frequency
Horizontal output pulse duty cycle
Horizontal pull-in range
PAL vertical free-running
oscillation frequency
NTSC vertical free-running
oscillation frequency
Vertical output pulse width
PAL vertical pull-in range
NTSC vertical pull-in range
Horizontal output voltage (H)
Horizontal output voltage (L)
8
f
HO
τ
HO
f
HP
f
VO-P
f
VO-N
τ
VO
f
VP-P
f
VP-N
V
56H
V
56L
Without sync. signal input
Upward going pulse duty cycle
Difference from f
H
=
15.625 kHz
Data 01−D7
=
1, 02−D7
=
0
Forced 50 Hz mode, no sync. signal input
Data 01−D7
=
1, 02−D7
=
1
Forced 60 Hz mode, no sync. signal input
For both PAL/NTSC
f
H
=
15.625 kHz, forced 50 Hz mode
f
H
=
15.75 kHz, forced 60 Hz mode
High-level DC voltage
Low-level DC voltage
15.33 15.63 15.93
31
±500
48
58
9
46
56
2.9
37
±650
50
60
10
3.2
43
52
62
11
54
64
3.5
0.3
kHz
%
Hz
Hz
Hz
1/fH
Hz
Hz
V
V