AN2018S
Correlated Double Sampling IC
s
Overview
The AN2018S is used to reduce noise in CCD im-
age sensor output signal. It performs correlated double-
sampling on image signal sent from a CCD sensor to
output clearer image signal.
0.1±0.1
0.4
0.4±0.25
5.0±0.3
0.3
4.2±0.3
6.5±0.3
8-Pin SOP Package (SOP008-P-0225)
Unit:mm
1.27
• Operating on low voltage (V
CC
=4.8V), consuming
little current (I
CC
=12.7mA typ.)
• Including a high-speed sampling circuit responding
to 510-830H CCD
• 6dB or 9dB fixed gain
• 83-dB high S/N-ratio (at 6dB output)
p
s
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
Pin name
CDS output (9dB)
Blanking pulse input
CCD signal input
V
CC
Sampling pulse input (2)
Sampling pulse input (1)
GND
CDS output (6dB)
s
Block Diagram
6dB OUT
8
GND
7
SP1
6
SP2
5
+
6dB
+
9dB
–
–
BLK
S/H
BIAS
50kΩ
S/H
1
2
3
4
9dB OUT
BLK
SIG.IN
V
CC
0.15
0.65
s
Features
1.5±0.2
PANASONIC [ PANASONIC SEMICONDUCTOR ]
