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74LVC1G32GW 参数 Datasheet PDF下载

74LVC1G32GW图片预览
型号: 74LVC1G32GW
PDF下载: 下载PDF文件 查看货源
内容描述: 单路2输入或门 [Single 2-input OR gate]
分类和应用: 逻辑集成电路光电二极管
文件页数/大小: 14 页 / 83 K
品牌: PANASONIC [ PANASONIC SEMICONDUCTOR ]
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Philips Semiconductors
Product specification
Single 2-input OR gate
FEATURES
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
• ±24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
2.5 ns.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay
inputs A, B to output Y
CONDITIONS
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 kΩ
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
V
CC
= 5.0 V; C
L
= 50 pF; R
L
= 500
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
input capacitance
power dissipation capacitance per buffer V
CC
= 3.3 V; notes 1 and 2
DESCRIPTION
74LVC1G32
The 74LVC1G32 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Input can be driven from either 3.3 V or 5 V devices. This
feature allow the use of these devices in a mixed
3.3 V and 5 V environment.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall time.
This device is fully specified for partial power-down
applications using I
off
. The I
off
circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G32 provides the single 2-input OR function.
TYPICAL
3.1
2.1
2.5
2.1
1.7
5
16
ns
ns
ns
ns
ns
UNIT
pF
pF
2004 Sep 15
2