Silicon MOS FETs (Small Signal)
P
D
Ta
1.6
1.2
Copper foil of the drain portion
should have a area of 1cm
2
or more and the board
thickness should be 1.7mm.
Ta=25˚C
1.0
V
GS
=5.5V
1.0
2SK601
I
D
V
DS
1.2
V
DS
=10V
Ta=25˚C
I
D
V
GS
Allowable power dissipation P
D
(W)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
20
40
Drain current I
D
(A)
0.8
5V
Drain current I
D
(A)
0.8
0.6
4.5V
0.6
0.4
4V
0.4
3.5V
0.2
3V
0
60
80 100 120 140 160
0
2
4
6
8
10
0
0
2
4
6
8
10
0.2
Ambient temperature Ta (˚C)
Drain to source voltage V
DS
(V)
Gate to source voltage V
GS
(V)
| Y
fs
|
V
GS
Input capacitance (Common source), Output capacitance (Common source),
Reverse transfer capacitance (Common source) C
iss
,C
oss
,C
rss
(pF)
600
C
iss
, C
oss
, C
rss
V
DS
V
DS
=15V
f=1kHz
Ta=25˚C
V
GS
=0
f=1MHz
Ta=25˚C
R
DS(on)
V
GS
Drain to source ON-resistance R
DS(on)
(
Ω
)
6
I
D
=500mA
5
120
Forward transfer admittance |Y
fs
| (mS)
500
100
400
80
4
300
60
3
Ta=75˚C
2
25˚C
–25˚C
200
40
C
iss
100
20
C
oss
0
1
3
10
30
C
rss
100
300
1000
1
0
0
1
2
3
4
5
6
0
0
4
8
12
16
20
Gate to source voltage V
GS
(V)
Drain to source voltage V
DS
(V)
Gate to source voltage V
GS
(V)
R
DS(on)
Ta
Drain to source ON-resistance R
DS(on)
(
Ω
)
6
I
D
=500mA
5
4
V
GS
=5V
3
10V
2
1
0
–50
–25
0
25
50
75
Ambient temperature Ta (˚C)
2
PANASONIC [ PANASONIC SEMICONDUCTOR ]
