Oxford Semiconductor, Inc.
USB to Quad Serial Port Bridge Data Sheet
(1)
Clock source selector; must be one of:
C0
0—PCLK=X1, RCLK=X1
1—PCLK=2/3 X1, RCLK=X1 (default)
CD
Configuration disable; must be one of:
0—configuration by software allowed
1—configuration by software disallowed
This is a sticky bit used to lock the configuration by writing to it from within the
boot PROM code
Note:
1
X1 input pin must be 12 MHz when using the PLL.
Breakpoint
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]
Offset: 0x0C014
Reset: 0x00
Read/write
This register holds the breakpoint address. Accessing this register
generates an interrupt.
A[15:0]
Breakpoint address
UARTControl
Offset: 0x0C0E0
Reset: 0x00
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Div8 B[2] B[1] B[0]
Read/write
This register facilitates debugging over the UART serial debugging
interface.
Div8
Pre-scaler trigger; used in conjunction with B[2:0]. Must be one of:
0—not used
1—used
If the pre-scaler is used, its effect is to divide the input clock by 8 to generate
the UART clock
B[2:0]
Baud rate selector; see Table 2 on page 7 for details
Table 2 Debug UART Baud Rates
B[2:0] Bit Setting
Baud Rate (Kbaud)
Baud Rate with Div8
Pre-Scaler (Kbaud)
000
001
010
011
100
101
110
115.2
57.6
38.4
28.8
19.2
14.4
9.6
14.4
7.2
4.8
3.6
2.4
1.8
1.2
DS-0016 Oct 06
External—Free Release
7
OXFORD [ OXFORD SEMICONDUCTOR ]
