Oxford Semiconductor, Inc.
OXU210HP Data Sheet
Figure 1 shows the OXU210HP block diagram.
Figure 1 OXU210HP Block Diagram
XSCI
PLL/
72 KB
Buffer
Test
Superior
TEST
Clock
Control
Performance
Large internal RAM
allows for multi-
buffering
XSCO
Memory
Transaction
Translator
ACK
DRQ
simultaneous
DMA
streams. Retries due
to USB NAKs are
done in hardware -
decreasing interrupts
and lowering CPU
and bus utilization.
Interface
HS
OTG
Xcvr
Host
Controller
2 Ports
Power
allow multiple usage
models:
Management
Transaction
Translator
2 Hosts
Low Power
Host + Peripheral, or
Host + OTG
Design
Multiple power and
clock regions are
available with
software-controlled
power saving modes.
PLL and oscillator
can be disabled for
deep-sleep state.
Clock control block
produces the lowest
of four primary clock
16/32-bit
Microprocessor
Interface
ADDR
DATA
Host
Controller
HS
OTG
Xcvr
Peripheral
Controller
System
Configuration &
Control Registers
CNTRL
INT
OTG
Controller
frequesncies that meet
the application’s
operational
Simultaneous Operation
Full host controller and peripheral
controller implementations allow both
to operate at the same time.
requirements.
OTG Logic
Integrated hardware or software
HNP options allw for more
control of your software
development.
Sample
Applications
Digital televisions
Home media centers
Portable media centers
Digital video cameras
Digital still cameras
Printers
MP3 players
External storage products
Set‐Top Boxes (STB)
Personal Video Recorders (PVR)
Personal Digital Assistants (PDA)
3G mobile phones
DVD recorders
DS-0037 Jun 06
External--Free Release
3
OXFORD [ OXFORD SEMICONDUCTOR ]
