OXmPCI954
OXFORD SEMICONDUCTOR LTD.
8.3.2
8.4
8.4.1
SOFTWARE RESET..................................................................................................................................................... 66
TRANSMITTER & RECEIVER FIFOS .............................................................................................................................. 67
FIFO CONTROL REGISTER ‘FCR’ .............................................................................................................................. 67
LINE CONTROL & STATUS............................................................................................................................................. 68
FALSE START BIT DETECTION.................................................................................................................................. 68
LINE CONTROL REGISTER ‘LCR’............................................................................................................................... 68
LINE STATUS REGISTER ‘LSR’ .................................................................................................................................. 69
INTERRUPTS & SLEEP MODE........................................................................................................................................ 70
INTERRUPT ENABLE REGISTER ‘IER’....................................................................................................................... 70
INTERRUPT STATUS REGISTER ‘ISR’....................................................................................................................... 71
INTERRUPT DESCRIPTION ........................................................................................................................................ 71
SLEEP MODE............................................................................................................................................................... 72
MODEM INTERFACE ....................................................................................................................................................... 72
MODEM CONTROL REGISTER ‘MCR’........................................................................................................................ 72
MODEM STATUS REGISTER ‘MSR’ ........................................................................................................................... 73
OTHER STANDARD REGISTERS ................................................................................................................................... 73
DIVISOR LATCH REGISTERS ‘DLL & DLM’................................................................................................................ 73
SCRATCH PAD REGISTER ‘SPR’ ............................................................................................................................... 73
AUTOMATIC FLOW CONTROL....................................................................................................................................... 74
ENHANCED FEATURES REGISTER ‘EFR’................................................................................................................. 74
SPECIAL CHARACTER DETECTION.......................................................................................................................... 75
AUTOMATIC IN-BAND FLOW CONTROL ................................................................................................................... 75
AUTOMATIC OUT-OF-BAND FLOW CONTROL ......................................................................................................... 75
8.5
8.5.1
8.5.2
8.5.3
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.7
8.7.1
8.7.2
8.8
8.8.1
8.8.2
8.9
8.9.1
8.9.2
8.9.3
8.9.4
8.10 BAUD RATE GENERATION............................................................................................................................................. 76
8.10.1
8.10.2
8.10.3
8.10.4
8.10.5
GENERAL OPERATION............................................................................................................................................... 76
CLOCK PRESCALER REGISTER ‘CPR’...................................................................................................................... 76
TIMES CLOCK REGISTER ‘TCR’................................................................................................................................. 76
EXTERNAL 1X CLOCK MODE..................................................................................................................................... 78
CRYSTAL OSCILLATOR CIRCUIT .............................................................................................................................. 78
8.11 ADDITIONAL FEATURES ................................................................................................................................................ 78
8.11.1
8.11.2
8.11.3
8.11.4
8.11.5
8.11.6
8.11.7
8.11.8
8.11.9
ADDITIONAL STATUS REGISTER ‘ASR’ .................................................................................................................... 78
FIFO FILL LEVELS ‘TFL & RFL’ ................................................................................................................................... 79
ADDITIONAL CONTROL REGISTER ‘ACR’................................................................................................................. 79
TRANSMITTER TRIGGER LEVEL ‘TTL’ ...................................................................................................................... 80
RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’ ...................................................................................................... 80
FLOW CONTROL LEVELS ‘FCL’ & ‘FCH’.................................................................................................................... 80
DEVICE IDENTIFICATION REGISTERS...................................................................................................................... 80
CLOCK SELECT REGISTER ‘CKS’.............................................................................................................................. 81
NINE-BIT MODE REGISTER ‘NMR’............................................................................................................................. 81
8.11.10 MODEM DISABLE MASK ‘MDM’.................................................................................................................................. 82
8.11.11 READABLE FCR ‘RFC’................................................................................................................................................. 82
8.11.12 GOOD-DATA STATUS REGISTER ‘GDS’.................................................................................................................... 82
8.11.13 PORT INDEX REGISTER ‘PIX’..................................................................................................................................... 82
8.11.14 CLOCK ALTERATION REGISTER ‘CKA’..................................................................................................................... 83
9
LOCAL BUS ........................................................................................................................................84
OVERVIEW ....................................................................................................................................................................... 84
OPERATION ..................................................................................................................................................................... 84
CONFIGURATION & PROGRAMMING............................................................................................................................ 85
9.1
9.2
9.3
10
BIDIRECTIONAL PARALLEL PORT...............................................................................................86
10.1 OPERATION AND MODE SELECTION ........................................................................................................................... 86
10.1.1
10.1.2
10.1.3
10.1.4
SPP MODE ................................................................................................................................................................... 86
PS2 MODE.................................................................................................................................................................... 86
EPP MODE ................................................................................................................................................................... 86
ECP MODE ................................................................................................................................................................... 86
10.2 PARALLEL PORT INTERRUPT....................................................................................................................................... 87
DS-0019 Jun 05 External—Free Release Page 4
OXFORD [ OXFORD SEMICONDUCTOR ]
