OXmPCI952
OXFORD SEMICONDUCTOR LTD.
6.6
INTERRUPTS & SLEEP MODE........................................................................................................................................ 57
INTERRUPT ENABLE REGISTER ‘IER’....................................................................................................................... 57
INTERRUPT STATUS REGISTER ‘ISR’....................................................................................................................... 58
INTERRUPT DESCRIPTION ........................................................................................................................................ 58
SLEEP MODE............................................................................................................................................................... 59
MODEM INTERFACE ....................................................................................................................................................... 59
MODEM CONTROL REGISTER ‘MCR’........................................................................................................................ 59
MODEM STATUS REGISTER ‘MSR’ ........................................................................................................................... 60
OTHER STANDARD REGISTERS ................................................................................................................................... 60
DIVISOR LATCH REGISTERS ‘DLL & DLM’................................................................................................................ 60
SCRATCH PAD REGISTER ‘SPR’ ............................................................................................................................... 60
AUTOMATIC FLOW CONTROL....................................................................................................................................... 61
ENHANCED FEATURES REGISTER ‘EFR’................................................................................................................. 61
SPECIAL CHARACTER DETECTION.......................................................................................................................... 62
AUTOMATIC IN-BAND FLOW CONTROL ................................................................................................................... 62
AUTOMATIC OUT-OF-BAND FLOW CONTROL ......................................................................................................... 62
6.6.1
6.6.2
6.6.3
6.6.4
6.7
6.7.1
6.7.2
6.8
6.8.1
6.8.2
6.9
6.9.1
6.9.2
6.9.3
6.9.4
6.10 BAUD RATE GENERATION............................................................................................................................................. 63
6.10.1
6.10.2
6.10.3
6.10.4
6.10.5
GENERAL OPERATION............................................................................................................................................... 63
CLOCK PRESCALER REGISTER ‘CPR’...................................................................................................................... 63
TIMES CLOCK REGISTER ‘TCR’................................................................................................................................. 63
EXTERNAL 1X CLOCK MODE..................................................................................................................................... 65
CRYSTAL OSCILLATOR CIRCUIT .............................................................................................................................. 65
6.11 ADDITIONAL FEATURES ................................................................................................................................................ 65
6.11.1
6.11.2
6.11.3
6.11.4
6.11.5
6.11.6
6.11.7
6.11.8
6.11.9
ADDITIONAL STATUS REGISTER ‘ASR’ .................................................................................................................... 65
FIFO FILL LEVELS ‘TFL & RFL’ ................................................................................................................................... 66
ADDITIONAL CONTROL REGISTER ‘ACR’................................................................................................................. 66
TRANSMITTER TRIGGER LEVEL ‘TTL’ ...................................................................................................................... 67
RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’ ...................................................................................................... 67
FLOW CONTROL LEVELS ‘FCL’ & ‘FCH’.................................................................................................................... 67
DEVICE IDENTIFICATION REGISTERS...................................................................................................................... 67
CLOCK SELECT REGISTER ‘CKS’.............................................................................................................................. 68
NINE-BIT MODE REGISTER ‘NMR’............................................................................................................................. 68
6.11.10 MODEM DISABLE MASK ‘MDM’.................................................................................................................................. 69
6.11.11 READABLE FCR ‘RFC’................................................................................................................................................. 69
6.11.12 GOOD-DATA STATUS REGISTER ‘GDS’.................................................................................................................... 69
6.11.13 PORT INDEX REGISTER ‘PIX’..................................................................................................................................... 69
6.11.14 CLOCK ALTERATION REGISTER ‘CKA’..................................................................................................................... 70
7
LOCAL BUS ........................................................................................................................................71
OVERVIEW ....................................................................................................................................................................... 71
OPERATION ..................................................................................................................................................................... 71
CONFIGURATION & PROGRAMMING............................................................................................................................ 72
7.1
7.2
7.3
8
BIDIRECTIONAL PARALLEL PORT ..................................................................................................73
OPERATION AND MODE SELECTION ........................................................................................................................... 73
SPP MODE ................................................................................................................................................................... 73
PS2 MODE.................................................................................................................................................................... 73
EPP MODE ................................................................................................................................................................... 73
ECP MODE ................................................................................................................................................................... 73
PARALLEL PORT INTERRUPT....................................................................................................................................... 74
REGISTER DESCRIPTION............................................................................................................................................... 75
PARALLEL PORT DATA REGISTER ‘PDR’................................................................................................................. 75
ECP FIFO ADDRESS / RLE ......................................................................................................................................... 75
DEVICE STATUS REGISTER ‘DSR’ ............................................................................................................................ 75
DEVICE CONTROL REGISTER ‘DCR’......................................................................................................................... 76
EPP ADDRESS REGISTER ‘EPPA’ ............................................................................................................................. 76
EPP DATA REGISTERS ‘EPPD1-4’ ............................................................................................................................. 76
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
DS-0020 Jun 05
Page 4
OXFORD [ OXFORD SEMICONDUCTOR ]
